r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 402

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Direct Memory Access Controller (DMAC)
9.3.7
The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers.
When the reload function is enabled, the RDMATCR value is written to the transfer count register
(DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA
transfer can be preset in RDMATCR during the current DMA transfer. When the reload function
is disabled, RDMATCR is ignored.
The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0.
As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when
H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in
16 bytes, one 16-byte transfer (128 bits) counts one.
RDMATCR is initialized to H'00000000 by a power-on reset and retains the value in manual reset,
software standby mode, and module standby mode.
Rev. 2.00 Dec. 09, 2005 Page 378 of 1152
REJ09B0191-0200
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Reload Transfer Count Registers (RDMATCR)
R/W
31
15
R
0
0
-
-
R/W
30
14
R
0
0
-
-
R/W
29
13
R
0
0
-
-
R/W
28
12
R
0
0
-
-
R/W
27
11
R
0
0
-
-
R/W
26
10
R
0
0
-
-
R/W
25
R
0
9
0
-
-
R/W
24
R
0
8
0
-
-
R/W
R/W
23
0
7
0
-
-
R/W
R/W
22
0
6
0
-
-
R/W
R/W
21
0
5
0
-
-
R/W
R/W
20
0
4
0
-
-
R/W
R/W
19
0
3
0
-
-
R/W
R/W
18
0
2
0
-
-
R/W
R/W
17
0
0
1
-
-
R/W
R/W
16
0
0
0
-
-