r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 821

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
4
3
2
1
0
Bit Name
NAKIE
STIE
ACKE
ACKBR
ACKBT
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
Description
NACK Receive Interrupt Enable
Enables or disables the NACK detection interrupt
request (NAKI) and the overrun error (OVE set in ICSR)
interrupt request (ERI) in the clocked synchronous
format when the NACKF or AL/OVE bit in ICSR is set.
NAKI can be canceled by clearing the NACKF, AL/OVE,
or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
Stop Condition Detection Interrupt Enable
Enables or disables the stop condition detection
interrupt request (STPI) when the STOP bit in ICSR is
set.
0: Stop condition detection interrupt request (STPI) is
1: Stop condition detection interrupt request (STPI) is
Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
1: If the receive acknowledge bit is 1, continuous
Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot
be modified. This bit can be canceled by setting the
BBSY bit in ICCR2 to 1.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at
the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
disabled.
enabled.
and continuous transfer is performed.
transfer is halted.
Rev. 2.00 Dec. 09, 2005 Page 797 of 1152
Section 16 I
2
C Bus Interface 3 (IIC3)
REJ09B0191-0200