r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 765

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
1
Bit Name
RDF
Initial
Value
0
R/W
R/(W)* Receive FIFO Data Full
Section 15 Serial Communication Interface with FIFO (SCIF)
Description
Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the
quantity of data in SCFRDR has become more than
the receive trigger number specified by the RTRG[1:0]
bits in the FIFO control register (SCFCR).
0: The quantity of transmit data written to SCFRDR is
[Clearing conditions]
•
•
•
1: The quantity of receive data in SCFRDR is more
[Setting condition]
•
Note: 1. As SCFTDR is a 16-byte FIFO register, the
less than the specified receive trigger number
than the specified receive trigger number
RDF is cleared to 0 by a power-on reset, standby
mode
RDF is cleared to 0 when the SCFRDR is read
until the quantity of receive data in SCFRDR
becomes less than the specified receive trigger
number after 1 is read from RDF and then 0 is
written
RDF is cleared to 0 when DMAC is activated by
receive FIFO data full interrupt (RXI) and read
SCFRDR until the quantity of receive data in
SCFRDR becomes less than the specified receive
trigger number
RDF is set to 1 when a quantity of receive data
more than the specified receive trigger number is
stored in SCFRDR*
maximum quantity of data that can be read
when RDF is 1 becomes the specified
receive trigger number. If an attempt is made
to read after all the data in SCFRDR has
been read, the data is undefined. The
quantity of receive data in SCFRDR is
indicated by the lower 8 bits of SCFDR.
Rev. 2.00 Dec. 09, 2005 Page 741 of 1152
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REJ09B0191-0200