r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 65

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Addressing
Mode
Register indirect
with
displacement
Register indirect
with
displacement
Indexed register
indirect
GBR indirect
with
displacement
Instruction
Format
@(disp:4,
Rn)
@(disp:12,
Rn)
@(R0,Rn)
@(disp:8,
GBR)
Effective Address Calculation
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
The effective address is the sum of Rn and a 12-
bit
displacement (disp). The value of disp is zero-
extended.
The effective address is the sum of Rn and R0.
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged for
a byte operation, is doubled for a word operation,
and is quadrupled for a longword operation.
(zero-extended)
(zero-extended)
(zero-extended)
1/2/4
Rn
R0
disp
GBR
1/2/4
disp
Rn
disp
Rn
×
×
+
+
+
+
Rn + disp × 1/2/4
+ disp × 1/2/4
Rn + disp
Rn + R0
Rev. 2.00 Dec. 09, 2005 Page 41 of 1152
GBR
REJ09B0191-0200
Equation
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
Rn + R0
Byte:
GBR + disp
Word:
GBR + disp × 2
Longword:
GBR + disp × 4
Section 2 CPU