r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 818

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.3.3
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
ICMR is initialized to H'38 by a power-on reset. Bits BC[2:0] are initialized to H'0 by the IICRST
bit in ICCR2.
Rev. 2.00 Dec. 09, 2005 Page 794 of 1152
REJ09B0191-0200
Bit
7
6
5, 4
3
I
2
Bit Name
MLS


BCWP
2
C Bus Mode Register (ICMR)
C Bus Interface 3 (IIC3)
Initial value:
Initial
Value
0
0
All 1
1
R/W:
Bit:
R/W
MLS
7
0
R/W
R/W
R
R
R/W
R
6
0
-
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Reserved
This bit is always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
BC Write Protect
Controls the BC[2:0] modifications. When modifying the
BC[2:0] bits, this bit should be cleared to 0. In clocked
synchronous serial mode, the BC[2:0] bits should not
be modified.
0: When writing, values of the BC[2:0] bits are set.
1: When reading, 1 is always read.
R
5
1
-
When writing, settings of the BC[2:0] bits are invalid.
R
4
1
-
BCWP
R/W
3
1
R/W
2
0
BC[2:0]
R/W
1
0
2
C bus format is used.
R/W
0
0