r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 337

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
(b) Self-refreshing
Self-refresh mode in which the refresh timing and refresh addresses are generated within the
SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR
to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion
of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which
number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM cannot be accessed
while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After
self-refresh mode has been cleared, command issuance is disabled for the number of cycles
specified by the WTRC1 and WTRC0 bits in CS3WCR.
Self-refresh timing is shown in figure 8.30. Settings must be made so that self-refresh clearing and
data retention are performed correctly, and auto-refreshing is performed at the correct intervals.
When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting
standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is
set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition
from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be
taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less
than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using the LSI standby function, and is maintained even after recovery from standby mode
due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby
state by setting the HIZCNT bit in CMNCR to 1.
The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state
controller's registers are initialized, and therefore the self-refresh state is cleared.
Rev. 2.00 Dec. 09, 2005 Page 313 of 1152
REJ09B0191-0200