r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 253

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
20
19
18 to 16
15 to 13
Bit Name
MPXW
BAS

WW[2:0]

Initial
Value
0
0
0
000
All 0
R/W
R/W
R/W
R
R/W
R
Description
MPX-I/O Interface Address Wait
This bit setting is valid only when area 5 is specified as
MPX-I/O. Specifies the address cycle insertion wait for
MPX-I/O interface.
0: Inserts no wait cycle
1: Inserts 1 wait cycle
SRAM with Byte Selection Byte Access Select
This bit setting is valid only when area 5 is specified as
SRAM with byte selection.
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read access cycle
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
asserts the RD/WR signal during the write access
cycle.
and asserts the RD/WR signal at the write timing.
read access wait cycles)
Rev. 2.00 Dec. 09, 2005 Page 229 of 1152
Section 8 Bus State Controller (BSC)
REJ09B0191-0200