r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 393

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
28
27 to 24
23
22
21, 20
Bit Name
RLD

DO
TL

Initial
Value
0
All 0
0
0
All 0
R/W
R/W
R
R/W
R/W
R
Descriptions
Reload Function Enable or Disable
Enables or disables the reload function.
0: Disables the reload function
1: Enables the reload function
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 to
CHCR_3. This bit is reserved in CHCR_4 and
CHCR_7; it is always read as 0 and the write value
should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
Transfer End Level
Specifies the TEND signal output is high active or low
active. This bit is valid only in CHCR_0 and CHCR_1.
This bit is reserved in CHCR_2 to CHCR_7; it is
always read as 0 and the write value should always be
0.
0: Low-active output from TEND
1: High-active output from TEND
Reserved
These bits are always read as 0. The write value
should always be 0.
Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 Dec. 09, 2005 Page 369 of 1152
REJ09B0191-0200