r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 68

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
Rev. 2.00 Dec. 09, 2005 Page 44 of 1152
REJ09B0191-0200
Addressing
Mode
Immediate
Instruction
Format
#imm:20
#imm:8
#imm:8
#imm:8
#imm:3
Effective Address Calculation
The 20-bit immediate data (imm) for the MOVI20
instruction is sign-extended.
The 20-bit immediate data (imm) for the MOVI20S
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits are
padded with zero.
Sign-extended
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
The 3-bit immediate data (imm) for the BAND, BOR,
BXOR, BST, BLD, BSET, and BCLR instructions
indicates the target bit location.
31
extended imm (20 bits)
Sign-
31 27
imm (20 bits) 00000000
19
8
0
0
Equation
—
—
—
—
—
—