r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 112

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 4 Exception Handling
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
Rev. 2.00 Dec. 09, 2005 Page 88 of 1152
REJ09B0191-0200
Type
Interrupt
Instruction
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BRAF.
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Exception Handling
On-chip peripheral modules
Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction*
instructions*
instruction)
3
, RESBANK instruction, DIVS instruction, and DIVU
1
, instructions that rewrite the PC*
Multi-function timer pulse unit 2S (MTU2S)
Port output enable 2 (POE2): OEI3
interrupt
I
Serial communication interface with FIFO
(SCIF)
2
C bus interface 3 (IIC3)
2
, 32-bit
Priority
High
Low

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