r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1169

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Numerics
16-bit/32-bit displacement ........................ 39
A
A/D conversion time
(multi mode and scan mode)................... 847
A/D conversion time (single mode)........ 846
A/D conversion timing ........................... 846
A/D converter (ADC) ............................. 827
A/D converter activation......................... 591
A/D converter characteristics................ 1119
A/D converter start request delaying
function................................................... 573
A/D trigger input timing ....................... 1114
Absolute address....................................... 39
Absolute address accessing....................... 39
Absolute maximum ratings................... 1059
AC characteristics................................. 1066
AC characteristics measurement
conditions ............................................. 1118
Access size and data alignment .............. 265
Access wait control................................. 273
Address array.................................. 180, 194
Address array read .................................. 194
Address errors........................................... 97
Address map ........................................... 204
Address multiplexing.............................. 284
Address-array write
(associative operation) ............................ 195
Address-array write
(non-associative operation)..................... 194
Addressing modes..................................... 40
Analog input pin ratings ......................... 852
Arithmetic operation instructions ............. 58
Auto-refreshing....................................... 311
Auto-request mode ................................. 387
Index
B
Bank active ............................................. 304
Banked register and input/output of
banks ....................................................... 150
Bit manipulation instructions .................... 66
Bit synchronous circuit ........................... 824
Block diagram............................................. 7
Branch instructions ................................... 63
Break detection and processing............... 782
Break on data access cycle...................... 173
Break on instruction fetch cycle.............. 172
Burst mode.............................................. 400
Burst MPX-I/O interface......................... 338
Burst read................................................ 296
Burst ROM (clocked asynchronous)
interface .................................................. 324
Burst ROM (clocked synchronous)
interface .................................................. 343
Burst write............................................... 301
Bus arbitration......................................... 351
Bus state controller (BSC) ...................... 199
Bus timing............................................. 1073
Bus-released state...................................... 68
C
Cache ...................................................... 179
Calculating exception handling vector
table addresses .......................................... 92
Canceling software standby mode
(WDT)..................................................... 714
Cascaded operation ................................. 508
Caution on period setting ........................ 606
Changing the division ratio ....................... 84
Changing the frequency .................... 83, 715
Changing the multiplication rate............... 83
Clock frequency control circuit................. 71
Rev. 2.00 Dec. 09, 2005 Page 1145 of 1152
REJ09B0191-0200