r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 750

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.1
SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is
automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
15.3.2
SCFRDR is a 16-byte FIFO register that stores serial receive data. The SCIF completes the
reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is initialized to an undefined value by a power-on reset.
Rev. 2.00 Dec. 09, 2005 Page 726 of 1152
REJ09B0191-0200
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
R
7
7
-
-
-
R
6
6
-
-
-
R
5
5
-
-
-
R
4
4
-
-
-
R
3
3
-
-
-
R
2
2
-
-
-
R
1
1
-
-
-
R
0
0
-
-
-