AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 96

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

switches the device to DWord I/O mode. A read access
other than listed in the table below will yield undefined
data; a write operation may cause unexpected repro-
gramming of the Am79C978A control registers. Table
28 shows legal I/O accesses in Word I/O mode.
Double Word I/O Mode
The Am79C978A controller can be configured to oper-
ate in DWord (32-bit) I/O mode. The software can invoke
the DWIO mode by performing a DWord write access
96
Table 27. I/O Map in Word I/O Mode (DWIO = 0)
00h - 0Fh
18h - 1Fh
AD[4:0]
Offset
0XX00
0XX01
0XX10
0XX11
0XX00
0XX10
0XX00
0XX10
10000
10010
10100
10110
10000
10010
10100
10110
10000
10h
12h
14h
16h
No. of
Bytes
16
2
2
2
2
8
BE[3:0]
1110
1101
1011
0111
1100
0011
1100
0011
1100
0011
1100
0011
1100
0011
1100
0011
0000
RAP (shared by RDP and BDP)
Table 28. Legal I/O Accesses in Word I/O Mode (DWIO = 0)
Type
Reset Register
WR
WR
WR
WR
WR
WR
WR
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
Reserved
Register
APROM
RDP
BDP
Byte read of APROM location 0h, 4h, 8h, or Ch
Byte read of APROM location 1h, 5h, 9h, or Dh
Byte read of APROM location 2h, 6h, Ah, or Eh
Byte read of APROM location 3h, 7h, Bh, or Fh
Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h, or
Ch and Dh
Word read of APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah, or
Fh and Eh
Word read of RDP
Word read of RAP
Word read of Reset Register
Word read of BDP
Word write to APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h, or
Ch and Dh
Word write to APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah, or
Fh and Eh
Word write to RDP
Word write to RAP
Word write to Reset Register
Word write to BDP
DWord write to RDP,
switches device to DWord I/O mode
Am79C978A
to the I/O location at offset 10h (RDP). The data of the
write access must be such that it does not affect the
intended operation of the Am79C978A controller. Set-
ting the device into 32-bit I/O mode is usually the first
operation after H_RESET or S_RESET. The RAP reg-
ister will point to CSR0 at that time. Writing a value of 0
to CSR0 is a safe operation. DWIO (BCR18, bit 7) will
be set to 1 as an indication that the Am79C978A con-
troller operates in 32-bit I/O mode.
Note: Even though the I/O resource mapping changes
when the I/O mode setting changes, the RDP location
offset is the same for both modes. Once the DWIO bit
has been set to 1, only H_RESET can clear it to 0. The
DWIO mode setting is unaffected by S_RESET or set-
ting of the STOP bit. Table 29 shows how the 32 bytes
of address space are used in DWord I/O mode.
All I/O resources must be accessed in DWord quantities
and on DWord addresses. A read access other than
listed in Table 30 will yield undefined data, a write op-
eration may cause unexpected reprogramming of the
Am79C978A control registers.
Comment