AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 57

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

When FASTSPNDE is 0 and the SPND bit is set, the
Am79C978A controller may take longer before enter-
ing the suspend mode. At the time the SPND bit is set,
the Am79C978A controller will complete the DMA pro-
cess of a transmit packet if it had already begun, and
the Am79C978A controller will completely receive a re-
ceive packet if it had already begun. TheAm79C978A
controller will not receive any new packets after the
completion of the current reception. Additionally, all
transmit packets stored in the transmit FIFOs and the
transmit buffer area in the SRAM (if one is present) will
be transmitted, and all receive packets stored in the re-
ceive FIFOs and the receive buffer area in the SRAM
(if selected) will be transferred into system memory.
Since the FIFO and the SRAM contents are flushed, it
may take much longer before the Am79C978A control-
ler enters the suspend mode. The amount of time that
it takes depends on many factors including the size of
the SRAM, bus latency, and network traffic level.
Upon completion of the described operations, the
Am79C978A controller sets the read-version of SPND
to 1 and enters the suspend mode. In suspend mode,
all of the CSR and BCR registers are accessible. As
long as the Am79C978A controller is not reset while in
suspend mode (by H_RESET, S_RESET, or by setting
the STOP bit), no re-initialization of the device is re-
quired after the device comes out of suspend mode.
When SPND is set to 0, the Am79C978A controller will
leave the suspend mode and will continue at the trans-
mit and receive descriptor ring locations where it was
when it entered the suspend mode.
See the section on Magic Packet technology for de-
tails on how that affects suspension of the integrated
Ethernet controller.
Buffer Management
Buffer management is accomplished through mes-
sage descriptor entries organized as ring structures
in memory. There are two descriptor rings, one for
transmit and one for receive. Each descriptor de-
scribes a single buffer. A frame may occupy one or
more buffers. If multiple buffers are used, this is re-
ferred to as buffer chaining.
Descriptor Rings
Each descriptor ring must occupy a contiguous area of
memory. During initialization, the user-defined base
address for the transmit and receive descriptor rings,
as well as the number of entries contained in the de-
scriptor rings are set up. The programming of the soft-
ware style (SWSTYLE, BCR20, bits 7-0) affects the
way the descriptor rings and their entries are arranged.
When SWSTYLE is at its default value of 0, the de-
scriptor rings are backwards compatible with the
Am79C90 C-LANCE and the Am79C96x PCnet-ISA
family. The descriptor ring base addresses must be
aligned to an 8-byte boundary and a maximum of 128
Am79C978A
ring entries is allowed when the ring length is set
through the TLEN and RLEN fields of the initialization
block. Each ring entry contains a subset of the three
32-bit transmit or receive message descriptors (TMD,
RMD) that are organized as four 16-bit structures
(SSIZE32 (BCR20, bit 8) is set to 0). Note that even
though the Am79C978A controller treats the descriptor
entries as 16-bit structures, it will always perform 32-bit
bus transfers to access the descriptor entries. The
value of CSR2, bits 15-8, is used as the upper 8-bits for
all memory addresses during bus master transfers.
When SWSTYLE is set to 2 or 3, the descriptor ring
base addresses must be aligned to a 16-byte bound-
ary, and a maximum of 512 ring entries is allowed when
the ring length is set through the TLEN and RLEN fields
of the initialization block. Each ring entry is organized
as three 32-bit message descriptors (SSIZE32
(BCR20, bit 8) is set to 1). The fourth DWord is re-
served. When SWSTYLE is set to 3, the order of the
message descriptors is optimized to allow read and
write access in burst mode.
For any software style, the ring lengths can be set
beyond this range (up to 65535) by writing the trans-
mit and receive ring length registers (CSR76,
CSR78) directly.
Each ring entry contains the following information:
n The address of the actual message data buffer in
n The length of the message buffer
n Status information indicating the condition of the
To permit the queuing and de-queuing of message
buffers, ownership of each buffer is allocated to either
the Am79C978A controller or the host. The OWN bit
within the descriptor status information, either TMD or
RMD, is used for this purpose.
When OWN is set to 1, it signifies that the Am79C978A
controller currently has ownership of this ring descrip-
tor and its associated buffer. Only the owner is permit-
ted to relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner
of a descriptor entry cannot assume ownership or
change any field in the entry. A device may, however,
read from a descriptor that it does not currently own.
Software should always read descriptor entries in se-
quential order. When software finds that the current de-
scriptor is owned by the Am79C978A controller, then
the software must not read ahead to the next descrip-
tor. The software should wait at a descriptor it does not
own until the Am79C978A controller sets OWN to 0 to
release ownership to the software. When LAPPEN
(CSR3, bit 5) is set to 1, this rule is modified. See the
LAPPEN description. At initialization, the Am79C978A
controller reads the base address of both the transmit
user or host memory
buffer
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