AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 113

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR3: Interrupt Masks and Deferral Control
Bit
31-16
15-13
12
11
10
9
8
7
Name
RES
RES
MISSM
MERRM
RINTM
TINTM
IDONM
RES
This bit is always read/write ac-
cessible. MISSM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
This bit is always read/write ac-
cessible. MERRM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
This bit is always read/write ac-
cessible. RINTM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
This bit is always read/write ac-
cessible. TINTM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
This bit is always read/write ac-
cessible. IDONM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zero.
Missed Frame Mask. If MISSM is
set, the MISS bit will be masked
and unable to set the INTR bit.
Memory Error Mask. If MERRM
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Receive Interrupt Mask. If RINTM
is set, the RINT bit will be masked
and unable to set the INTR bit.
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Reserved location. Read and
written as zero.
Interrupt
Done
Mask.
Mask.
Am79C978A
If
If
6
5
DXSUFLO
LAPPEN
flow error.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C978A controller graceful-
ly recovers from an UFLO error.
It scans the transmit descriptor
ring until it finds the start of a
new frame and starts a new
transmission.
This bit is always read/write ac-
cessible. DXSUFLO is cleared by
H_RESET or S_RESET and is
not affected by STOP.
Enable. When set to a 1, the
LAPPEN bit will
Am79C978A controller to gener-
ate an interrupt following the de-
scriptor write operation to the first
buffer of a receive frame. This in-
terrupt will be generated in addi-
tion to the interrupt that is
generated following the descrip-
tor write operation to the last buff-
er of a receive packet. The
interrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a 1 also en-
ables the Am79C978A control-
ler to read the STP bit of receive
descriptors. The Am79C978A
controller will use the STP infor-
mation to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the Am79C978A
controller can write intermediate
packet data to buffers whose
descriptors do not contain STP
bits set to 1. Following the write
to the last descriptor used by a
packet, the Am79C978A con-
troller will scan through the next
descriptor entries to locate the
next STP bit that is set to a 1.
The Am79C978A controller will
begin writing the next packets
data to the buffer pointed to by
that descriptor.
Disable Transmit Stop on Under-
Look Ahead Packet Processing
cause the
113