AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 136

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

11-10 XMTSP[1:0] Transmit Start Point. XMTSP
136
Table 33. Receive Watermark Programming
RCVFW[1:0]
00
01
10
11
present in the FIFO before re-
ceive DMA is requested.
When operating with the SRAM,
the Bus Receive FIFO, and the
MAC Receive FIFO operate inde-
pendently on the bus side and
MAC side of the SRAM, respec-
tively. In this case, the watermark
value set by RCVFW[1:0] sets the
number of bytes that must be
present in the Bus Receive FIFO
only. See Table 33.
These bits are read/write accessi-
ble only when either the STOP or
the SPND bit is set. RCVFW[1:0] is
set to a value of 01b (64 bytes) af-
ter H_RESET or S_RESET and is
unaffected by STOP.
controls the point at which pream-
ble transmission attempts to com-
mence in relation to the number
of bytes written to the MAC
Transmit FIFO for the current
transmit frame. When the entire
frame is in the MAC Transmit
FIFO, transmission will start re-
gardless of the value in XMTSP.
If the network interface is operat-
ing in half-duplex mode, regard-
less of XMTSP, the FIFO will not
internally overwrite its data until
at least 64 bytes (or the entire
frame if shorter than 64 bytes)
have been transmitted onto the
network. This ensures that for
collisions within the slot time win-
dow, transmit data need not be
rewritten to the Transmit FIFO,
and retries will be handled auton-
omously by the MAC. If the Dis-
able Retry feature is enabled, or if
the network is operating in full-du-
plex mode, the Am79C978A con-
troller
beginning of the frame as soon as
Bytes Received
can
Reserved
112
16
64
overwrite
Am79C978A
the
9-8
XMTSP[1:0]
Table 34. Transmit Start Point Programming
XX
00
01
10
00
01
10
11
11
XMTFW[1:0] Transmit
SRAM_SIZE
the data is transmitted, because
no collision handling is required in
these modes.
Note that when the SRAM is be-
ing used, if the NOUFLO bit
(BCR18, bit 11) is set to 1, there
is the additional restriction that
the complete transmit frame must
be DMA’d into the Am79C978A
controller and reside within a
combination of the Bus Transmit
FIFO, the SRAM, and the MAC
Transmit FIFO.
When the SRAM is used and
SRAM_SIZE > 0, there is a re-
striction that the number of bytes
written is a combination of bytes
written into the Bus Transmit
FIFO and the MAC Transmit
FIFO. The Am79C978A control-
ler supports a mode that will wait
until a full packet is available be-
fore commencing with the trans-
mission of preamble. This mode
is useful in a system where high
latencies cannot be avoided. See
Table 34.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. XMTSP is
set to a value of 01b (64 bytes)
after H_RESET or S_RESET
and is unaffected by STOP.
XMTFW specifies the point at
which transmit DMA is request-
ed, based upon the number of
bytes that could be written to the
>0
>0
>0
>0
>0
0
0
0
0
FIFO
NOUFLO bit is set
Full Packet when
Bytes Written
Full Packet
220 max
128
128
20
64
36
64
Watermark.