AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 108

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

14-13 DATA_SCALE
12-9
8
7-2
1-0
108
PWR_STATEPower State. This 2-bit field is
RESReserved locations. These bits are read
PME_ENPME Enable. When a 1, PME_EN en-
DATA_SEL Data Select. This optional 4-bit
Data Scale. This 2-bit read-only
field indicates the scaling factor
to be used when interpreting the
value of the Data register. The
value and meaning of this field
will vary
DATA_SCALE field.
These bits are read only.
field is used to select which data
is reported through the Data reg-
ister and DATA_SCALE field.
These bits are always read/write
accessible. Sticky bit. These bits
are reset by POR. H_RESET,
S_RESET, or setting the STOP
bit has no effect.
ables the function to assert PME.
When a 0, PME assertion is dis-
abled.
This bit defaults to “0” if the func-
tion does not support PME gener-
ation from D3
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating
loaded.
This bit is always read/write ac-
cessible. Sticky bit. This bit is re-
set
S_RESET, or setting the STOP
bit has no effect.
only.
used both to determine the cur-
rent power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
00b - D0
01b - D1
10b - D2
11b - D3
by
depending on the
system
POR.
cold
.
is
H_RESET,
initially
Am79C978A
PCI PMCSR Bridge Support Extensions Register
Offset 46h
Bit
7-0
PCI Data Register
Offset 47h
Note: All bits of this register are loaded from the
EEPROM. The register is aliased to lower bytes of the
BCR37-BCR44 for testing purposes.
Bit
7-0
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C978A controller. The RAP contains the address
of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
PMCSR_BSE The PCI PMCSR Bridge Support
Name
Name
DATA_REG The PCI Data Register is an 8-bit
read, but their contents have no
effect on the operation of the
device.
accessible.
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
Extensions register is located at
offset 46h in the PCI Configura-
tion Space. These bits are read
only.
register. Refer to the “PCI Bus
Power Management Interface
Specification” version 1.0 for a
more detailed description of this
register.
offset 47h in the PCI Configuration
Space. It is read only.
These bits can be written and
These bits are always read/write
Description
The PCI PMCSR Bridge Support
Description
The PCI DATA register s located at