AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 163

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

BCR25: SRAM Size Register
Bit
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8
7-0
SRAM_SIZE SRAM Size. Specifies the upper 8
RES
Name
The value of SID is up to the sys-
tem vendor. A value of 0 (the de-
fault)
Am79C978A controller does not
support subsystem identification.
SID is aliased to the PCI configu-
ration space register Subsystem
ID (offset 2Eh).
This bit is always read accessible.
SID is read only. Write operations
are ignored. SID is cleared to 0 by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
Reserved locations. Written as
zeros and read as undefined.
bits of the 16-bit total size of the
SRAM
SRAM_SIZE accounts for a 512-
byte page. The starting address
for the lower 8 bits is assumed to
be 00h and the ending address for
the lower is assumed to be FFh.
Therefore, the maximum address
range is the starting address of
0000h to ending address of
((SRAM_SIZE+1) * 256 words)) or
17FFh. An SRAM_SIZE value of
all zeros specifies that no SRAM
will be used and the internal
FIFOs will be joined into a contig-
uous FIFO similar to the PCnet-
PCI II controller.
Note: The minimum allowed
number of pages is eight for nor-
mal
Am79C978A controller will not
operate correctly with less than
the eight pages of memory.
When the minimum number of
pages is used, these pages must
be allocated four each for trans-
mit and receive.
CAUTION:
SRAM_BND and SRAM_SIZE
to the same value will cause
Description
network
indicates
buffer.
operation.
Each
Programming
that
bit
Am79C978A
The
the
in
BCR26: SRAM Boundary Register
Bit
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8
7-0
Maximum SRAM_BND Address
SRAM_BND SRAM Boundary. Specifies the
Minimum SRAM_BND
RES
Table 42. SRAM_BND Programming
SRAM Addresses
Name
Address
upper 8 bits of the 16-bit address
boundary where the receive buffer
begins in the SRAM. The transmit
buffer in the SRAM begins at ad-
dress 0 and ends at the address
located just before the address
specified by SRAM_BND. There-
fore, the receive buffer always be-
gins on a 512 byte boundary. The
lower bits are assumed to be ze-
ros. SRAM_BND has no effect in
the Low Latency Receive mode.
data corruption except in the
case where SRAM_SIZE is 0.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set. SRAM_SIZE
is
H_RESET and is unaffected by
S_RESET or STOP.
Reserved locations. Written as
zeros and read as undefined.
Note: The minimum allowed
number of pages is four. The
Am79C978A controller will not
operate correctly with less than
four pages of memory per queue.
See Table 42 for SRAM_BND
programming details.
CAUTION:
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM SIZE is 0.
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_BND is set to
00000000b
Description
set
to
during
SRAM_BND [7:0]
000000b
Programming
04h
13h
H_RESET
during
163