AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 56

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Buffer Management Unit
The Buffer Management Unit (BMU) is a microcoded
state machine which implements the initialization pro-
cedure and manages the descriptors and buffers. The
buffer management unit operates at half the speed of
the CLK input.
Initialization
Initialization includes the reading of the initialization
block in memory to obtain the operating parameters.
The initialization block can be organized in two ways.
When SSIZE32 (BCR20, bit 8) is at its default value
of 0, all initialization block entries are logically 16-
bits wide to be backwards compatible with the
Am79C90 C-LANCE and Am79C96x PCnet-ISA
family. When SSIZE32 (BCR20, bit 8) is set to 1, all
initialization block entries are logically 32-bits wide.
Note that the Am79C978A controller always per-
forms 32-bit bus transfers to read the initialization
block entries. The initialization block is read when
the INIT bit in CSR0 is set. The INIT bit should be set
before or concurrent with the STRT bit to insure cor-
rect operation. Once the initialization block has been
completely read in and internal registers have been
updated, IDON will be set in CSR0, generating an in-
terrupt (if IENA is set).
TheAm79C978A controller obtains the start address of
the initialization block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most signifi-
cant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for operation, to-
gether with the base addresses and length information
of the transmit and receive descriptor rings.
Ther e is an alter nate method to initialize the
Am79C978A controller. Instead of initialization via
the initialization block in memory, data can be writ-
ten directly into the appropriate registers. Either
method or a combination of the two may be used
at the discretion of the programmer. Refer to Ap-
pendix A, Alternative Method for Initialization for
details on this alternate method.
Re-Initialization
Th e t ra n s m i tt e r a n d r e c e i ve r s ec ti o n s o f t h e
Am79C978A controller can be turned on via the initial-
ization block (DTX, DRX, CSR15, bits 1-0). The states
of the transmitter and receiver are monitored by the
h o s t t h r o u g h C S R 0 ( R X O N , T X O N b i t s ) .
TheAm79C978A controller should be re-initialized if
the transmitter and/or the receiver were not turned on
during the original initialization and it was subsequently
required to activate them, or if either section was shut
off due to the detection of an error condition (MERR,
UFLO, TX BUFF error).
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Am79C978A
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the Am79C978A controller as in the C-LANCE de-
vice. In particular, upon restart, the Am79C978A con-
troller reloads the transmit and receive descriptor
pointers with their respective base addresses. This
means that the software must clear the descriptor
OWN bits and reset its descriptor ring pointers before
restarting the Am79C978A controller. The reload of de-
scriptor base addresses is performed in the C-LANCE
device only after initialization, so that a restart of the C-
LANCE without initialization leaves the C-LANCE
pointing at the same descriptor locations as before the
restart.
Suspend
TheAm79C978A controller offers two suspend modes
that allow easy updating of the CSR registers without
going through a full re-initialization of the device. The
suspend modes also allow stopping the device with
orderly termination of all network activity.
The host requests the Am79C978A controller to enter
the suspend mode by setting SPND (CSR5, bit 0) to
1. The host must poll SPND until it reads back 1 to de-
termine that the Am79C978A controller has entered
the suspend mode. When the host sets SPND to 1,
the procedure taken by the Am79C978A controller to
enter the suspend mode depends on the setting of the
fast suspend enable bit (FASTSPND, CSR7, bit 15).
When a fast suspend is requested (FASTSPND is
set to 1), the Am79C978A controller performs a
quick entry into the suspend mode. At the time the
SPND bit is set, the Am79C978A controller will con-
tinue the DMA process of any transmit and/or re-
ceive packets that have already begun DMA activity
until the network activity has been completed. In ad-
dition, any transmit packet that had started transmis-
sion will be fully transmitted and any receive packet
that had begun reception will be fully received. How-
ever, no additional packets will be transmitted or re-
ceived and no additional transmit or receive DMA
activity will begin after network activity has ceased.
Hence, the Am79C978A controller may enter the
suspend mode with transmit and/or receive packets
still in the FIFOs or the SRAM. This offers a worst
case suspend time of a maximum length packet over
the possibility of completely emptying the SRAM.
Care must be exercised in this mode, because the
entire memory subsystem of the Am79C978A con-
troller is suspended. Any changes to either the de-
s c r i p t o r r i n g s o r t h e S R A M c a n c a u s e t h e
Am79C978A controller to start up in an unknown
condition and could cause data corruption.