AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 114

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

114
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1, the Am79C978A controller will
advance through the receive de-
scriptor ring regardless of the
state of ownership bits. If any of
the entries that are examined
during
Am79C978A controller owner-
ship of the descriptor but also in-
dicate
Am79C978A controller will reset
the OWN bit to 0 in these entries.
If a scanned entry indicates host
ownership with STP = 0, then the
Am79C978A controller will not al-
ter the entry, but will advance to
the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the Am79C978A controller, then
the Am79C978A controller will
stop advancing through the ring
entries and begin periodic polling
of this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the Am79C978A con-
troller, then the controller will stop
advancing through the ring en-
tries, store the descriptor infor-
mation that it has just read, and
wait for the next receive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header portion of a receive pack-
et will always be written to a par-
ticular memory area, and the data
portion of a receive packet will al-
ways be written to a separate
memory area. The interrupt is
generated when the header bytes
have been written to the header
memory area.
this
STP = 0,
search
then
indicate
Am79C978A
the
4
3
2
DXMT2PD Disable Transmit Two Part Defer-
EMBA
BSWP
This bit is always read/write ac-
cessible. The LAPPEN bit will be
reset to 0 by H_RESET or
S_RESET and will be unaffected
by STOP.
See Appendix B for more infor-
mation on the Look Ahead Pack-
et Processing concept.
ral (see Medium Allocation sec-
tion
Management section for more
details). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
This bit is always read/write ac-
cessible. DXMT2PD is cleared by
H_RESET or S_RESET and is
not affected by STOP.
rithm (see the Contention Reso-
lution section in Media Access
Management section for more
details). If EMBA is set, a modi-
fied
implemented.
This bit is always read/write ac-
cessible. EMBA is cleared by
H_RESET or S_RESET and is
not affected by STOP.
choose between big and little
Endian modes of operation.
When BSWP is set to a 1, big
Endian mode is selected. When
BSWP is set to 0, little Endian
mode is selected.
When big Endian mode is select-
ed, the Am79C978A controller will
swap the order of bytes on the AD
bus during a data phase on ac-
cesses to the FIFOs only. Specifi-
cally, AD[31:24] becomes Byte 0,
AD[23:16]
AD[15:8] becomes Byte 2, and
AD[7:0] becomes Byte 3 when big
Endian mode is selected. When
little Endian mode is selected, the
order of bytes on the AD bus dur-
ing a data phase is: AD[31:24] is
Byte 3, AD[23:16] is Byte 2,
Enable Modified Back-off Algo-
Byte Swap. This bit is used to
in
back-off
the
becomes
Media
algorithm
Byte
Access
1,
is