AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 173

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

9-8
7-0
BCR44: PCI DATA Register 7 (DATA7) Alias Register
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR44 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corre-
sponding fields pointed with the DATA_SEL field set to
seven. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
15-10 RES
9-8
7-0
D6_SCALE
DATA6
Name
D7_SCALE
DATA7
These bits correspond to the
DATA_SCALE field of the PMCSR
(offset Register 44 of the PCI con-
figuration space, bits 14-13). Refer
to the description of DATA_SCALE
for the meaning of this field.
These bits are always read ac-
cessible. D6_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read ac-
cessible. DATA6 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Description
Reserved locations. Written as
zeros and read as undefined.
These bits correspond to the
DATA_SCALE field of the PMCSR
(offset Register 44 of the PCI con-
figuration space, bits 14-13). Refer
to the description of DATA_SCALE
for the meaning of this field.
These bits are always read ac-
cessible. D7_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
These bits correspond to the PCI
DATA register (offset register 47
of the PCI configuration space,
bits 7-0). Refer to the description
Am79C978A
BCR45: OnNow Pattern Matching Register 1
Note: This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
Bit
31-16 RES
15-8
7 PMAT_MODE
Name
PMR_B0
Description
Reserved locations. Written as
Pattern Match Mode. Writing a 1
of DATA register for the meaning
of this field.
These bits are always read ac-
cessible. DATA7 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
zeros and read as undefined.
Pattern Match RAM Byte 0. This
byte is written into or read from
Byte 0 of the Pattern Match RAM.
These bits are read and write ac-
cessible always. PMR_B0 is un-
defined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
to this bit will enable Pattern
Match Mode and should only be
done after the Pattern Match
RAM has been programmed.
These bits are read and write ac-
cessible always. PMAT_MODE is
reset to 0 after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
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