AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 107

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

10
9
8-6
5
D2_SPT
D1_SPT
AUX_CURRENT
DSI
D2 Support. If this bit is a 1, this
function supports the D2 Power
Management State.
This bit is read only.
D1 Support. If this bit is a 1, this
function supports the D1 Power
Management State.
This bit is read only.
Auxiliary Current Requirements.
This
3.3Vaux current requirements for
the PCI function. If the Data Reg-
ister has been implemented by
this function, then reads of this
field must return a value of 000b
and the Data Register will take
precedence over this field for
3.3Vaux
reporting.
If PME generation from D3
not supported by the function
(PMC (15) = 0), this field must re-
turn a value of 000b when read.
For functions that support PME
from D3
the Data Register, the following
bit assignments apply:
These bits are read only.
Device
When this bit is 1, it indicates that
special initialization of the func-
tion is required (beyond the stan-
dard PCI configuration header)
8 7 6
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Bit
3-bit
cold
Specific
Max. Current Required
current
and do not implement
field
0 (self-powered)
3.3Vaux
375 mA
320 mA
270 mA
220 mA
160 mA
100 mA
55 mA
reports
Initialization.
requirement
cold
Am79C978A
the
is
4
3
2-0
PCI Power Management Control/Status Register
(PMCSR)
Offset 44h
Bit
15
PME_STATUS PME Status. This bit is set when
RES
PME_CLK
PMIS_VER Power Management Interface
Name
before the generic class device
driver is able to use it.
it indicates that the function relies
on the presence of the PCI clock
for PME operation. When this bit
is a 0 it indicates that no PCI
clock is required for the function
to generate PME.
PME generation in any state
must return 0 for this field.
Specification Version. A value of
001b indicates that this function
complies with revision 1.0 of the
PCI
Interface Specification.
the function would normally as-
sert the PME signal independent
of the state of the PME_EN bit.
and cause the function to stop as-
serting a PME (if enabled).
Writing a 0 has no effect.
D3
must be explicitly cleared by the
operating system each time the
operating
loaded.
cessible. Sticky bit. This bit is re-
set
S_RESET, or setting the STOP
bit has no effect.
This bit is read only.
Reserved location.
PME Clock. When this bit is a 1,
Functions that do not support
This bit is read only.
Description
Writing a 1 to this bit will clear it
If the function supports PME from
This bit is always read/write ac-
cold
, then this bit is sticky and
by
Power
system
POR.
Management
is
H_RESET,
initially
107