AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 195

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Initialization Block
Note: When SSIZE32 (BCR20, bit 8) is set to 0, the
software structures are defined to be 16 bits wide. The
base address of the initialization block must be aligned
to a DWord boundary, i.e., CSR1, bit 1 and 0 must be
cleared to 0. When SSIZE32 is set to 0, the initialization
block looks like Table 76.
RLEN and TLEN
When SSIZE32 (BCR20, bit 8) is set to 0, the software
structures are defined to be 16 bits wide, and the RLEN
and TLEN fields in the initialization block are each three
bits wide. The values in these fields determine the num-
ber of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is shown in Table 78. If a value other than those
IADR+0Ch
IADR+00h
IADR+04h
IADR+08h
IADR+10h
IADR+14h
IADR+18h
Address
IADR+0Ah
IADR+0Ch
IADR+0Eh
IADR+00h
IADR+02h
IADR+04h
IADR+06h
IADR+08h
IADR+10h
IADR+12h
IADR+14h
IADR+16h
Address
31-28
TLEN
Bits
Bits 15-13
RLEN
TLEN
27-24
RES
Bits
Table 76. Initialization Block (SSIZE32 = 0)
Table 77. Initialization Block (SSIZE32 = 1)
RES
RLEN
23-20
Bits
Bit 12
0
0
Am79C978A
19-16
RES
Bits
LADRF 31-00
LADRF 63-32
RDRA 31-00
PADR 31-00
TDRA 31-00
Note: The Am79C978A controller performs DWord ac-
cesses to read the initialization block. This statement is
always true, regardless of the setting of the SSIZE32 bit.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide. The base ad-
dress of the initialization block must be aligned to a
DWord boundary, i.e., CSR1, bits 1 and 0 must be
cleared to 0. When SSIZE32 is set to 1, the initialization
block looks like Table 77.
listed in Table 79 is desired, CSR76 and CSR78 can be
written after initialization is complete.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide, and the RLEN
and TLEN fields in the initialization block are each four
bits wide. The values in these fields determine the num-
ber of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is shown in Table 79.
LADRF 15-00
LADRF 31-16
LADRF 47-32
LADRF 63-48
Bits 11-8
MODE 15-00
RDRA 15-00
PADR 15-00
PADR 31-16
PADR 47-32
TDRA 15-00
RES
RES
15-12
Bits
11-8
Bits
Bits 7-4
PADR 47-32
MODE
TDRA 23-16
TDRA 23-16
Bits
7-4
Bits 3-0
Bits
3-0
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