AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 26

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

TX_CLK
Transmit Clock
TX_CLK is a clock input that provides the timing ref-
erence for the transfer of the TXD[3:0] and TX_ER
signals into the Am79C978A device. TX_CLK must
provide a nibble rate clock (25% of the network data
rate). Hence, when the Am79C978A device is oper-
ating at 10 Mbps, it provides an TX_CLK frequency
of 2.5 MHz, and at 100 Mbps it provides an RX_CLK
frequency of 25 MHz.
TXD[3:0]
Transmit Data
TXD[3:0] is the nibble-wide MII-compatible transmit
data bus. Valid data is generated on TXD[3:0] on
every rising edge of TX_CLK while TX_EN is as-
serted. While TX_EN is deasserted, TXD[3:0] values
are driven to 0. TXD[3:0] transitions are synchronous
to rising edges of TX_CLK
TX_EN
Transmit Enable
TX_EN indicates when the Am79C978A device is pre-
senting valid transmit nibbles on the MII TXD[3:0] bus.
While TX_EN is asserted, the Am79C978A device
generates TXD[3:0] and TX_ER on TX_CLK rising
edges. TX_EN is asserted with the first nibble of pre-
amble and remains asserted throughout the duration
of the packet until it is deasserted prior to the first
TX_CLK following the final nibble of the frame. TX_EN
transitions are synchronous to TX_CLK.
MDC
Management Data Clock
MDC is the non-continuous clock output that provides a
timing reference for bits on the MDIO pin. During MII man-
agement port operations, MDC runs at a nominal fre-
quency of 2.5 MHz. When no management operations
are in progress, MDC is driven LOW.
If the MII port is not selected, the MDC pin may be
left floating.
MDIO
Management Data Input/Output
MDIO is a bidirectional MII management port data pin.
MDIO is an output during the header portion of the
management frame transfers and during the data por-
tion of write operations. MDIO is an input during the
data portion of read operations.
If a PHY is attached to the MII port via a MII physical
connector then the MDIO pin should be externally
pulled down to V
PHY is directly attached to the MII pins then the
26
ss
with a 10 K
±5% resistor. If a
Input/Output
Output
Output
Output
Input
Am79C978A
MDIO pin should be externally pulled up to V
a 10 k
IEEE 1149.1 (1990) Test Access Port
Interface
TCK
Test Clock
TCK is the clock input for the boundary scan test
mode operation. It can operate at a frequency of
up to10 MHz. TCK has an internal pull-up resistor.
TDI
Test Data In
TDI is the test data input path to the Am79C978A
controller. The pin has an internal pull-up resistor.
TDO
Test Data Out
T D O i s t h e t e s t d a t a o u t p u t p a t h f r o m t h e
Am79C978A controller. The pin is tri-stated when
the JTAG port is inactive.
TMS
Test Mode Select
A serial input bit stream on the TMS pin is used to de-
fine the specific boundary scan test to be executed.
The pin has an internal pull-up resistor.
Ethernet Network Interfaces
TX±
Serial Transmit Data
These pins carry the transmit output data and are connected
to the transmit side of the magnetics module.
RX±
Serial Receive Data
These pins accept the receive input data from the
magnetics module.
IREF
Internal Current Reference
This pin serves as a current reference for the inte-
grated 1/10 PHY. It must be connected to V
through a 12 k
PHY_RST
PHY Reset
This output is used to reset the external PHY. This output
eliminates the need for a fanout buffer on the PCI reset
(RST) signal, provided polarity control for the specific
PHY used, and prevents the resetting of the PHY when
the PG input is LOW. The output polarity is determined
by the RST_POL (CRS116, bit0).
±5% resistor.
resistor (1%).
Input
Input
Output
Output
Output
cc
Input
Input
Input
with
SS