AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 42

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Figure 17 shows a typical burst write access. The
Am79C978A controller arbitrates for the bus, is
granted ac cess, and wr ites four 32-bit wor ds
(DWords) to the system memory and then releases
the bus. In this example, the memory system ex-
tends the data phase of the first access by one wait
state. The following three data phases take one
clock cycle each, which is determined by the timing
of TRDY. The example assumes that EXTREQ
(BCR18, bit 8) is set to 1, therefore, REQ is not deas-
serted until the next to last data phase is finished.
Target Initiated Termination
When the Am79C978A controller is a bus master, the
cycles it produces on the PCI bus may be terminated
by the target in one of three different ways: disconnect
42
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
Figure 16. Non-Burst Write Transfer
2
ADDR
0111
3
Am79C978A
PAR
4
DATA
BE
with data transfer, disconnect without data transfer, and
target abort.
Disconnect With Data Transfer
Figure 18 shows a disconnection in which one last data
transfer occurs after the target asserted STOP. STOP
is asserted on clock 4 to start the termination se-
quence. Data is still transferred during this cycle, since
both IRDY and TRDY are asserted. The Am79C978A
controller terminates the current transfer with the deas-
sertion of FRAME on clock 5 and of IRDY one clock
later. It finally releases the bus on clock 7. If it wants to
transfer more data, the Am79C978A controller will
again request the bus after two clock cycles. The start-
ing address of the new transfer will be the address of
the next non-transferred data.
5
PAR
6
7
ADDR
0111
8
DATA
PAR
BE
9
PAR
10
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