AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 145

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

BCR2: Miscellaneous Configuration
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-14 RES
13
12
11-9
8
PHYSELEN This
LEDPE
RES
APROMWE Address PROM Write Enable.
Name
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written and
read as zeros.
BCR18[4:3] for software selec-
tion of various operation and
test modes. When PHYSELEN
is set to 0 (default), the two bits
can only be written from the
EEPROM. When PHYSELEN is
set to 1, writes to BCR18[4:3]
are enabled.
This bit is always read/write ac-
cessible. TSTSHDEN is cleared
to 0 by H_RESET and is unaffect-
ed by S_RESET or by setting the
STOP bit.
LED Program Enable. When
LEDPE is set to 1, programming
of the LED0 (BCR4), LED1
(BCR5), LED2 (BCR6), LED3
(BCR7), and LED4 (BCR48)
registers
LEDPE is cleared to 0, program-
ming of LED0 (BCR4), LED1
(BCR5), LED2 (BCR6), LED3
(BCR7), and LED4 (BCR48)
registers is disabled. Writes to
those registers will be ignored.
This bit is always read/write ac-
cessible. LEDPE is cleared to 0
by H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
Reserved locations. Written and
read as zeros.
The Am79C978A controller con-
tains a shadow RAM on board for
storage of the first 16 bytes load-
ed from the serial EEPROM.
Accesses to Address PROM I/O
Resources will be directed toward
this RAM. When APROMWE is
Description
bit
is
enables
enabled.
writes
When
Am79C978A
to
7
6-3
2-0
INTLEVEL
RES
RES
set to 1, then write access to the
shadow RAM will be enabled.
This bit is always read/write ac-
cessible. APROMWE is cleared
to 0 by H_RESET and is unaffect-
ed by S_RESET or by setting the
STOP bit.
Interrupt Level. This bit allows the
interrupt output signals to be pro-
grammed for level or edge-
sensitive applications.
When INTLEVEL is cleared to 0,
the INTA pin is configured for
level-sensitive applications. In
this mode, an interrupt request is
signaled by a low level driven on
the INTA pin by the Am79C978A
controller. When the interrupt is
cleared, the INTA pin is tri-stated
by the Am79C978A controller
and allowed to be pulled to a high
level by an external pullup de-
vice. This mode is intended for
systems which allow the interrupt
signal to be shared by multiple
devices.
When INTLEVEL is set to 1, the
INTA pin is configured for edge-
sensitive applications. In this
mode, an interrupt request is sig-
naled by a high level driven on
the INTA pin by the Am79C978A
controller. When the interrupt is
cleared, the INTA pin is driven to
a low level by the Am79C978A
controller. This mode is intended
for systems that do not allow in-
terrupt channels to be shared by
multiple devices.
INTLEVEL should not be set to 1
when the Am79C978A controller
is used in a PCI bus application.
This bit is always read/write ac-
cessible. INTLEVEL is cleared to
0 by H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written and
read as zeros.
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