AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet

AM79C978A

Manufacturer Part Number

AM79C978A

Description

Single-Chip 1/10 Mbps PCI Home Networking Controller

Manufacturer

AMD [Advanced Micro Devices]

Datasheet

1.AM79C978A.pdf (256 pages)

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Am79C978A

PCnet™- Home

Single-Chip 1/10 Mbps PCI Home Networking Controller

DISTINCTIVE CHARACTERISTICS

n Fully integrated 1 Mbps HomePNA Physical Layer

n Adjustable power and speed levels

n 32 bits of reserved in-band messaging

n Power control

n Performance registers

n Speed control

n Major frame timing parameters programmable:

n Fully integrated 10 Mbps PHY interface

n Integrated Fast Ethernet controller for the

(PHY) as defined by Home Phoneline Networking

Alliance (HomePNA) specification 1.1

— Optimized for home networking applications

— In-band control features

piggybacked on Ethernet packet

— Register programmable features

ISBI, AID ISBI, pulse width, inter-symbol time

— Comprehensive Auto-Negotiation

— Full-duplex capability

— Optimized for 10BASE-T applications

Peripheral Component Interconnect (PCI) bus

— 32-bit glueless PCI host interface

— Supports PCI clock frequency from DC to

— Supports network operation with PCI clock

— High performance bus mastering

— PCI draft specification revision 2.2 compliant

— Supports PCI Subsystem/Subvendor ID/

— Supports both PCI 5.0-V and 3.3-V

— Plug and Play compatible

— Supports an unlimited PCI burst length

over ordinary copper telephone wire

implementation

33 MHz independent of network clock

from 15 MHz to 33 MHz

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

Vendor ID programming through the

EEPROM interface

signaling environments

Refer to AMD’s Website (www.amd.com) for the latest information.

n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

n Compliant with HomePNA specification 1.1

n Media Independent Interface (MII) for

n Full-duplex operation supported on the MII port

n Supports PC98/PC99 and Net PC specifications

n Independent internal TX and RX FIFOs

— Big endian and little endian byte

— Implements optional PCI power management

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 Ethernet standard

connecting external 10/100 Mbps transceivers

— IEEE 802.3u compliant MII

— Intelligent Auto-Poll™ external PHY status

— Supports both auto-negotiable and non-

— Supports 10BASE-T, 100BASETX/FX,

with independent Transmit (TX) and Receive

(RX) channels

— Implements full OnNow features including

— Implements Magic Packet™ mode

— Magic Packet mode and the physical address

— Supports PCI Bus Power Management

— Supports Advanced Configuration and Power

— Supports Network Device Class Power

— Programmable FIFO watermarks for both TX

alignments supported

event (PME) pin

monitor and interrupt

auto-negotiable external PHYs

100BASET4, and 100BASET2 IEEE 802.3

compliant MII PHYs at full-duplex or half-

duplex

pattern matching and link status wake-up

events

loaded from EEPROM at power up without

requiring PCI clock

Interface specification revision 1.1

Interface (ACPI) specification version 1.0

Management specification version 1.0a

and RX operations

Publication# 22399

Issue Date: January 2000

Rev: C Amendment/0

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