AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 22

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

INTA
Interrupt Request
An attention signal which indicates that one or more
of the following status flags is set: EXDINT, IDON,
MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT,
TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT,
MREINT, and STINT. Each status flag has either a
mask or an enable bit which allows for suppression of
INTA assertion. Table 1 shows the flag descriptions.
By default INTA is an open-drain output. For applica-
tions that need a high-active edge-sensitive interrupt
signal, the INTA pin can be configured for this mode
by setting INTLEVEL (BCR2, bit 7) to Table 1.
When RST is active, INTA is the output for NAND
tree testing.
22
Name
EXDINT
IDON
MERR
MISS
MFCO
MPINT
RCVCCO
RINT
SINT
TINT
TXSTRT
UINT
MCCINT
MPDTINT
MAPINT
MREINT
STINT
Description
Excessive
Deferral
Initialization
Done
Memory Error
Missed Frame CSR3, bit 12 CSR0, bit 12
Missed Frame
Count Overflow
Magic Packet
Interrupt
Receive
Collision Count
Overflow
Receive
Interrupt
System Error
Transmit
Interrupt
Transmit Start
User Interrupt
MII
Management
Command
Complete
Interrupt
MII PHY Detect
Transition
Interrupt
MII Auto-Poll
Interrupt
MII
Management
Frame Read
Error Interrupt
Software Timer
Interrupt
Table 1. Interrupt Flags
Mask Bit
CSR5, bit 6
CSR3, bit 8
CSR3, bit 11 CSR0, bit 11
CSR4, bit 8
CSR5, bit 3
CSR4, bit 4
CSR3, bit 10 CSR0, bit 10
CSR5, bit 10 CSR5, bit 11
CSR3, bit 9
CSR4, bit 2
CSR4, bit 7
CSR7, bit 4
CSR7, bit 0
CSR7, bit 6
CSR7, bit 8
CSR7, bit 10 CSR7, bit 11
Interrupt Bit
CSR5, bit 7
CSR0, bit 8
CSR4, bit 9
CSR5, bit 4
CSR4, bit 5
CSR0, bit 9
CSR4, bit 3
CSR4, bit 6
CSR7, bit 5
CSR7, bit 1
CSR7, bit 7
CSR7, bit 9
Output
Am79C978A
IRDY
Initiator Ready
IRDY indicates the ability of the initiator of the transac-
tion to complete the current data phase. IRDY is used
in conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the Am79C978A controller is a bus master, it as-
serts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. During all read data
phases, the device asserts IRDY to indicate that it is
ready to accept the data.
When the Am79C978A controller is the target of a trans-
action, it checks IRDY during all write data phases to de-
termine if valid data is present on AD[31:0]. During all
read data phases, the device checks IRDY to determine
if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND
tree testing.
PAR
Parity
Parity is even parity across AD[31:0] and C/BE[3:0].
When the Am79C978A controller is a bus master, it
generates parity during the address and write data
phases. It checks parity during read data phases.
When the Am79C978A controller operates in slave
mode, it checks parity during every address phase.
When it is the target of a cycle, it checks parity during
write data phases and it generates parity during read
data phases.
When RST is active, PAR is an input for NAND
tree testing.
PERR
Parity Error
During any slave write transaction and any master read
transaction, the Am79C978A controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C978A controller monitors PERR to see if the
target reports a data parity error.
When RST is active, PERR is an input for NAND
tree testing.
REQ
Bus Request
The Am79C978A controller asserts REQ pin as a sig-
nal that it wishes to become a bus master. REQ is
driven high when the Am79C978A controller does not
request the bus. In Power Management mode, the
REQ pin will not be driven.
Input/Output
Input/Output
Input/Output
Input/Output