AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 164

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

BCR27: SRAM Interface Control Register
Bit
31-16 RES
15
14
164
PTR TST
LOLATRX
Name
and is unaffected by S_RESET or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved. Reserved for manu-
facturing tests. Written as zero
and read as undefined.
Note: Use of this bit will cause
data corruption and erroneous
operation.
This bit is always read/write ac-
cessible. PTR_TST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
Low Latency Receive. When the
LOLATRX bit is set to 1, the
Am79C978A controller will switch
to an architecture applicable to
cut-through
Am79C978A controller will assert
a receive frame DMA after only
16 bytes of the current receive
frame has been received regard-
less
(CSR80, bits 13-12) are set. The
watermark is a fixed value and
cannot be changed. The receive
FIFOs will be in NO_SRAM mode
while all transmit traffic is buff-
ered through the SRAM. This bit
is only valid and the low latency
receive o only enabled when the
SRAM_SIZE (BCR25, bits 7-0)
bits are non-zero. SRAM_BND
(BCR26, bits 7-0) has no mean-
ing when the Am79C978A con-
troller is in the Low Latency
mode. See the section on SRAM
Configuration for more details.
When the LOLATRX bit is set to
0, the Am79C978A controller will
return to a normal receive config-
uration. The runt packet accept
bit (RPA, CSR124, bit 3) must be
set when LOLATRX is set.
CAUTION: To provide data in-
tegrity when switching into and
out of the low latency mode, DO
Description
of
where
switches.
the
RCVFW
Am79C978A
The
13-6
5-3
EBCS
1XX
000
001
010
011
RES
EBCS
Table 43. EBCS Values
Expansion Bus Clock Source
Expansion Bus Clock Source.
NOT
(CSR7, bit 15) bit when setting
the SPND bit. Receive frames
WILL be overwritten and the
Am79C978A
give erratic behavior when it is
enable again. The minimum al-
lowed number of pages is four.
The Am79C978A controller will
not operate correctly in the
LOLATRX mode with less than
four pages of memory.
Read/Write accessible only when
the STOP bit is set. LOLATRX is
cleared to 0 after H_RESET or
S_RESET and is unaffected by
STOP.
Reserved locations. Written as
zeros and read as undefined.
These bits are used to select the
source of the fundamental clock
to drive the SRAM and Expansion
ROM access cycles. Table 43
shows the selected clock source
for the various values of EBCS.
Note that the actual frequency
that the Expansion Bus access
cycles run at is a function of both
the
(BCR27, bits 2-0) bit field set-
tings. When EBCS is set to either
the PCI clock or the Time Base
clock, no external clock source is
required as the clocks are routed
internally and the EBCLK pin
should be pulled to VDD through
a resistor.
Read accessible always; write
accessible only when the STOP
bit is set. EBCS is set to 000b
(PCI
H_RESET and is unaffected by
S_RESET or the STOP bit.
CLK pin (PCI Clock)
Time Base Clock
EBCS
EBCLK pin
SET
Reserved
Reserved
clock
the
selected)
controller
and
FASTSPNDE
CLK_FAC
during
may