AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 185

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

TBR17: 10BASE-T PHY Control/Status Register
(Register 17)
This register is used to control the configuration of the
10 Mbps PHY unit of the Am79C978A home network-
ing device. See Table 58.
Note:
1. For these loopback paths, the data is also transmitted out of the MDI pins (TX±).
Reg
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
Bits
8:7
15
14
13
12
11
10
9
6
5
4
3
2
1
0
SQE_TEST Disable
Table 58. TBR17: 10BASE-T PHY Control/Status Register (Register 17)
Extended Distance
Disable Link Pulse
Polarity Correction
Force Link Good
Receive Polarity
Jabber Detect
TX_DISABLE
Auto Receive
TX_CRS_EN
PHY Isolated
Reserved
Reserved
Reserved
Reserved
Reversed
Reserved
Disable
Disable
Enable
Enable
Name
1 = Link status forced to link up state
0 = Link status is determined by the device
1 = Link pulses sent from the
10BASE-T transmitter are suppressed
1 = Disables the SQE heartbeat which
occurs after each 10BASE-T transmission
0 = The heart beat assertion occurs on the
COL pin approximately 1 µs after
transmission and for a duration of 1 µs.
1 = Disable jabber detect
0 = Enable jabber detect
1 = Receive polarity of the 10BASE-T
receiver is reversed
0 = Receive polarity is correct
1 = Polarity correction circuit is disabled for
10BASE-T
0 = Self correcting polarity circuit is enabled
1 = 10BASE-T receive squelch thresholds
are reduced to allow reception of frames
which are greater than 100 meters
0 = Squelch thresholds are set for standard
distance of 100 meters
1 = TX± outputs not active for 10BASE-T.
TX± outputs to logical “0” for PECL.
0 = Transmit valid data
1 = CRS is asserted when transmit or
receive medium is active
0 = CRS is asserted when receive medium
is active
1 = Internal PHY is isolated
0 = Internal PHY is enabled
Am79C978A
Description
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Reset
H/W
0/1
00
0
0
0
0
0
0
0
0
0
0
0
0
0
Soft Reset
Previous
Previous
Retains
Retains
Value
Value
0/1
00
0
0
0
0
0
0
0
0
0
0
0
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