AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 125

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

2
1
LOOP
0
0
1
LOOP
DTX
Table 31. Loopback Configuration
INTL
0
0
0
MIIILP
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
This bit was called DTCR in the
LANCE (Am7990) device.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
When the APAD_XMT bit (CSR4,
bit11) is set to 1, the setting of
DXMTFCS has no effect.
Loopback Enable allows the
Am79C978A controller to oper-
ate in full-duplex mode for test
purposes. The setting of the
full-duplex control bits in BCR9
have no effect when the device
operates in loopback mode.
When LOOP = 1, loopback is
enabled. In combination with
INTL and MIIILP, various loop-
back modes are defined as fol-
lows in Table 31.
Disable
Am79C978A controller not ac-
cessing the Transmit Descriptor
Ring and, therefore, no transmis-
sions are attempted. DTX = 0,
will set TXON bit (CSR0 bit 4) if
STRT (CSR0 bit 1) is asserted.
Refer to Loopback Operation
section for more details.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and is
unaffected by STOP.
0
1
0
DXMTFCS
Normal Operation
Internal Loop
External Loop
Transmit
Function
is
results
set
Am79C978A
and
in
0
CSR16: Initialization Block Address Lower
Bit
31-16 RES
15-0
CSR17: Initialization Block Address Upper
Bit
31-16 RES
15-0
CSR18: Current Receive Buffer Address Lower
Bit
31-16 RES
15-0
DRX
Name
IADRL
Name
IADRH
Name
CRBAL
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
the Am79C978A controller not
accessing the Receive De-
scriptor Ring and, therefore,
all receive frame data are ig-
nored. DRX = 0 will set RXON
bit (CSR0 bit 5) if STRT
(CSR0 bit 1) is asserted.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
zeros and read as undefined.
current receive buffer address at
which the Am79C978A controller
will store incoming frame data.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Disable Receiver results in
Description
Reserved locations. Written as
This register is an alias of CSR1.
Description
Reserved locations. Written as
This register is an alias of CSR2.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
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