AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 118

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

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MPPLBA
MPINT
MPINTE
This bit is always read/write ac-
cessible. EXDINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
This bit is always read/write ac-
cessible. MPINT is cleared by the
host by writing a 1. Writing a 0
has no affect. MPINT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
This bit is always read/write ac-
cessible. MPINT is cleared to 0
Magic Packet Physical Logical
Broadcast Accept. If MPPLBA is
at its default value of 0, the
Am79C978A controller will only
detect a Magic Packet frame if
the destination address of the
packet matches the content of
the physical address register
(PADR). If MPPLBA is set to 1,
the destination address of the
Magic Packet frame can be uni-
cast, multicast, or broadcast.
Note that the setting of MPPLBA
only affects the address detection
of the Magic Packet frame. The
Magic Packet frame’s data se-
quence must be made up of 16
consecutive physical addresses
(PADR[47:0]) regardless of what
kind of destination address it has.
This bit is OR’ed with the
EMPPLBA bit (CSR116, bit 6).
This bit is always read/write ac-
cessible. MPPLBA is set to 0 by
H_RESET or S_RESET and is
not
STOP bit.
Magic Packet Interrupt. Magic
Packet Interrupt is set by the
Am79C978A controller when the
device is in Magic Packet mode
and the Am79C978A controller
receives a Magic Packet frame.
When MPINT is set to 1, INTA is
asserted if IENA (CSR0, bit 6)
and the enable bit MPINTE are
set to 1.
Magic Packet Interrupt Enable. If
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
affected
by
setting
Am79C978A
the
2
1
0
MPEN
MPMODE
SPND
by H_RESET or S_RESET and is
not affected by setting the STOP
bit.
lows activation of the Magic
Packet mode by the host. The
Am79C978A controller will enter
the Magic Packet mode when
both MPEN and MPMODE are
set to 1.
This bit is always read/write ac-
cessible. MPEN is cleared to 0 by
H_RESET or S_RESET and is
not
STOP bit.
enter the Magic Packet mode
when MPMODE is set to 1 and ei-
ther PG is asserted or MPEN is
set to 1.
This bit is always read/write ac-
cessible. MPMODE is cleared to
0 by H_RESET or S_RESET and
is not affected by setting the
STOP bit
cause the Am79C978A controller
to start requesting entrance into
suspend mode. The host must
poll SPND until it reads back 1 to
determine that the Am79C978A
controller has entered the sus-
pend mode. Setting SPND to 0
will get the Am79C978A control-
ler out of suspend mode. SPND
can only be set to 1 if STOP
(CSR0, bit 2) is set to 0.
H_RESET, S_RESET, or setting
the
Am79C978A controller out of
suspend mode.
Requesting entrance into the
suspend mode by the host de-
pends on the setting of the
FASTSPNDE bit (CSR7, bit 15).
Refer to the bit description of the
FASTSPNDE bit and the Sus-
pend section in Detailed Func-
tions, Buffer Management Unit
for details.
In suspend mode, all of the CSR
and BCR registers are accessi-
Magic Packet Enable. MPEN al-
The Am79C978A controller will
Suspend. Setting SPND to 1 will
affected
STOP
bit
by
will
setting
get
the
the