AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 159

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

3
2
RST Pin
EEDET Value
(BCR19[13])
High
High
High
Low
RES
ECS
0
0
1
1
Read in Progress
PREAD or Auto
Connected?
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. EEN is set to 0 by
H_RESET and is unaffected by
the S_RESET or STOP bit.
Reserved location. Written as
zero and read as undefined.
EEPROM Chip Select. This bit is
used to control the value of the
EECS pin of the interface when
the EEN bit is set to 1 and the
PREAD bit is set to 0. If EEN = 1
and PREAD = 0 and ECS is set to
a 1, then the EECS pin will be
forced to a HIGH level at the rising
EEPROM
X
1
0
0
Yes
Yes
No
No
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
Table 40. Interface Pin Assignment
Result if PREAD is Set to 1
EEN
X
X
1
0
Table 39. EEDET Setting
Am79C978A
Bit of BCR19
From ECS
EECS
Active
0
0
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
From ESK Bit of
Result of Automatic EEPROM Read
Operation Following H_RESET
Tri-State
BCR19
EESK
Active
edge of the next clock following bit
programming.
If EEN = 1 and PREAD = 0 and
ECS is set to a 0, then the EECS
pin will be forced to a LOW level
at the rising edge of the next
clock following bit programming.
ECS has no effect on the output
value of the EECS pin unless the
PREAD bit is set to 0 and the
EEN bit is set to 1.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. ECS is set to 0 by
H_RESET and is not affected by
S_RESET or STOP.
LED1
From EEDI Bit of
Tri-State
BCR19
Active
LED0
EEDI
159