AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 36

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Disconnect When Busy
The Am79C978A controller cannot service any slave
access while it is reading the contents of the EEPROM.
Simultaneous access is not allowed in order to avoid
conflicts, since the EEPROM is used to initialize some
of the PCI configuration space locations and most of
the BCRs and CSR116. The EEPROM read operation
will always happen automatically after the deassertion
of the RST pin. In addition, the host can start the read
operation by setting the PREAD bit (BCR19, bit 14).
While the EEPROM read is on-going, the Am79C978A
controller will disconnect any slave access where it is
the target by asserting STOP together with DEVSEL,
while driving TRDY high. STOP will stay asserted until
the end of the cycle.
Note that I/O and memory slave accesses will only be
disconnected if they are enabled by setting the IOEN or
MEMEN bit in the PCI Command register. Without the
enable bit set, the cycles will not be claimed at all. Since
H_RESET clears the IOEN and MEMEN bits for the au-
tomatic EEPROM read after H_RESET, the disconnect
only applies to configuration cycles.
A second situation where the Am79C978A controller will
generate a PCI disconnect/retry cycle is when the host
tries to access any of the I/O resources right after having
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DEVSEL
FRAME
STOP
TRDY
C/BE
IRDY
CLK
PAR
AD
1
DEVSEL is sampled
ADDR
CMD
2
Figure 7. Expansion ROM Read
PAR
3
BE
Am79C978A
4
5
read the Reset register. Since the access generates an
internal reset pulse of about 1 ms in length, all further
slave accesses will be deferred until the internal reset
operation is completed. See Figure 8.
Disconnect Of Burst Transfer
The Am79C978A controller does not support burst ac-
cess to the configuration space, the I/O resources, or
to the Expansion Bus. The host indicates a burst trans-
action by keeping FRAME asserted during the data
phase. When the Am79C978A controller sees FRAME
and IRDY asserted in the clock cycle before it wants to
assert TRDY, it also asserts STOP at the same time.
The transfer of the first data phase is still successful,
since IRDY and TRDY are both asserted. See Figure 9.
If the host is not yet ready when the Am79C978A con-
troller asserts TRDY, the device will wait for the host to
assert IRDY. When the host asserts IRDY and FRAME
is still asserted, the Am79C978A controller will finish
the first data phase by deasserting TRDY one clock
later. At the same time, it will assert STOP to signal a
disconnect to the host. STOP will stay asserted until
the host removes FRAME. See Figure 10.
48
49
DATA
50
PAR
51
22399A-10