AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 41

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Basic Non-Burst Write Transfer
By default, the Am79C978A controller uses non-
burst cycles in all bus master write operations. All
controller non-burst write accesses are of the PCI
command type Memory Write (type 7). The byte en-
able signals indicate the byte lanes that have valid
data. The Am79C978A controller typically performs
more than one non-burst write transaction within a
single bus mastership period. FRAME is dropped
between consecutive non-burst write cycles. REQ
stays asserted until FRAME is asserted for the last
transaction. The Am79C978A controller supports
zero wait state write cycles except with descriptor
write transfers. (See the Descriptor DMA Transfers
section for the only exception.) It asserts IRDY im-
mediately after the address phase.
Figure 16 shows two non-burst write transactions.
The first transaction has two wait states. The target
inserts one wait state by asserting DEVSEL one
clock late and another wait state by also asserting
TRDY one clock late. The second transaction
shows a zero wait state write cycle. The target as-
serts DEVSEL and TRDY in the same cycle as the
Am79C978A controller asserts IRDY.
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)
1
DEVSEL is sampled
2
ADDR
1110
3
PAR
4
Am79C978A
5
DATA
Basic Burst Write Transfer
The Am79C978A controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
Am79C978A controller must also be programmed to
use SWSTYLE 3 (BCR20, bits 7-0). All controller burst
write transfers are of the PCI command type Memory
Write (type 7). AD[1:0] will both be 0 during the address
phase indicating a linear burst order. The byte enable
signals indicate the byte lanes that have valid data.
The Am79C978A controller will always perform a sin-
gle burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The Am79C978A control-
ler supports zero wait state write cycles except with the
case of descriptor write transfers. (See the Descriptor
DMA Transfers section for the only exception.) The de-
vice asserts IRDY immediately after the address phase
and at the same time star ts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
6
0000
PAR
7
DATA
8
PAR
9
DATA
10
PAR
11
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