AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 176

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

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PSE
LNKSE
RCVME
XMTE
Receive Match Status Enable.
Am79C978A controller is func-
tioning in a Link Pass state and
full-duplex operation is en-
abled. When the Am79C978A
controller is not functioning in
a Link Pass state with full-du-
plex operation being enabled,
a value of 0 is passed to the
LEDOUT signal.
This bit is always read/write ac-
cessible. FDLSE is cleared by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new oc-
currence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
This bit is always read/write ac-
cessible. PSE is set to 1 by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
This bit is always read/write ac-
cessible. LNKSE is cleared by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
When this bit is set, a value of 1
is passed to the LEDOUT bit in
this register when there is re-
ceive activity on the network that
has passed the address match
function for this node. All ad-
dress matching modes are in-
cluded: physical, logical filtering,
broadcast, and promiscuous.
This bit is always read/write ac-
cessible. RCVME is cleared by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
Transmit Status Enable. When
this bit is set, a value of 1 is
Am79C978A
3
2
1
0
BCR49: PHY Select
This register defines which PHY will be able to send
and receive data over the MII interface. Bits 15:8 are
updated whenever the EEPROM is read, and bits 6:0
are updated only if bit 7 is cleared. The bits are defined
as follows:
Bit
15
14-10 RES
POWER
RCVE
SPEED
COLE
PC_NET
Name
Receive Status Enable. When
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
This bit is always read/write ac-
cessible. XMTE is cleared by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network.
This bit is always read/write ac-
cessible. RCVE is set to 1 by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
This bit is always read/write ac-
cessible. COLE is cleared by
H_RESET and is not affected
by S_RESET or setting the
STOP bit.
PCnet mode. This bit must al-
ways be set.
Reserved locations. These bits
must be written as zeros.
Description