AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 55

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Note that the Am79C978A controller will always per-
form a DWord transfer as long as it owns the buffer
space, even when there are less than four bytes to
write. For example, if there is only one byte left for
the current receive frame, the Am79C978A controller
will write a full DWord, containing the last byte of the
receive frame in the least significant byte position
(BSWP is cleared to 0, CSR3, bit 2). The content of
the other three bytes is undefined. The message
byte count in the receive descriptor always reflects
the exact length of the received frame.
TheAm79C978A controller will continue transferring
FIFO data until the transmit FIFO is filled to its high
threshold (read transfers) or the receive FIFO is emp-
tied to its low threshold (write transfers), or the
Am79C978A controller is preempted and the PCI La-
tency Timer is expired. The host should use the val-
ues in the PCI MIN_GNT and MAX_LAT registers to
determine the value for the PCI Latency Timer.
Figure 31. FIFO Burst Write at Start of Unaligned
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
Buffer
0111
ADD
3
DATA
0001
PAR
4
DATA
PAR
5
0000
22399A-34
DATA
PAR
6
Am79C978A
The exact number of total transfer cycles in the bus
mastership period is dependent on all of the following
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C978A controller’s bus request, and the
speed of bus operation. The TRDY response time of
the memory device will also affect the number of trans-
fers, since the speed of the accesses will affect the
state of the FIFO. During accesses, the FIFO may be
filling or emptying on the network end. For example, on
a receive operation, a slower TRDY response will allow
additional data to accumulate inside of the FIFO. If the
accesses are slow enough, a complete DWord may be-
come available before the end of the bus mastership
period and, thereby, increase the number of transfers
in that period. The general rule is that the longer the
Bus Grant latency, the slower the bus transfer opera-
tions; the slower the clock speed, the higher the trans-
mit watermark; or the lower the receive watermark, the
longer the total burst length will be.
When a FIFO DMA burst operation is preempted,
the Am79C978A controller will not relinquish bus
ownership until the PCI Latency Timer expires.
Figure 32. FIFO Burst Write at End of Unaligned
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
0111
ADD
Buffer
3
DATA
PAR
4
0000
DATA
PAR
5
DATA
1110
PAR
22399A-35
6
PAR
55
7