AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 94

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

STOP
A STOP reset is generated by the assertion of the STOP
bit in CSR0. Writing a 1 to the STOP bit of CSR0, when
the stop bit currently has a value of 0, will initiate a STOP
reset. If the STOP bit is already a 1, then writing a 1 to the
STOP bit will not generate a STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4 to
default values. For the identity of individual CSRs and bit
locations that are affected by STOP, see the individual
CSR register descriptions. STOP will not affect any of the
BCR and PCI configuration space locations. STOP will
cause the microcode program to jump to its reset state.
Following the end of the STOP operation, the controller
will not attempt to read the EEPROM device.
CAUTION:STOP will not cause a deassertion of the
REQ signal, if it happens to be active at the time of the
write to CSR0. The controller will wait until it gains bus
ownership, and it will first finish all scheduled bus mas-
ter accesses before the STOP reset is executed.
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to termi-
94
31
Base-Class
DATA_REG
MAX_LAT
Reserved
24
Subsystem ID
Device ID
Status
PMC
23
PMCSR_BSE
Header Type
Sub-Class
MIN_GNT
Reserved
Memory Mapped I/O Base Address
Expansion ROM Base Address
Table 26.
I/O Base Address
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCI Configuration Space Layout
Am79C978A
15
Programming IF
NXT_ITM_PTR
Latency Timer
Interrupt Pin
nate all network activity in an orderly sequence before
setting the STOP bit.
Power on Reset
Power on Reset (POR) is generated when the controller
is powered up. POR generates a hardware reset
(H_RESET). In addition, it clears some bits that
H_RESET does not affect.
Software Access
PCI Configuration Registers
The controller implements the 256-byte configuration
space as defined by the PCI draft specification revision
2.2. The 64-byte header includes all registers required to
identify the controller and its function. Additionally, PCI
Power Management Interface registers are implemented
at location 40h - 47h. The layout of the PCI configuration
space is shown in Table 26.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow lit-
tle endian byte ordering. All write accesses to Reserved
locations have no effect; reads from these locations will
return a data value of 0.
Subsystem Vendor ID
8
Command
Vendor ID
PMCSR
7
Interrupt Line
Revision ID
CAP-PTR
Reserved
CAP_ID
0
Offset
0Ch
1Ch
2Ch
3Ch
44H
FCh
14h
00h
04h
08h
10h
18h
20h
24h
28h
30h
34h
38h
40h
.
.