AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 140

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR116: OnNow Power Mode Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
10 PME_EN_OVR PME_EN Overwrite. When this
9
8
7
6
140
PMAT
LCDET
LCMODE
EMPPLBA
Name
Link Change Detected. This bit is
Link Change Wake-up Mode. When
Description
Reserved locations. Written as
zeros and read as undefined.
bit is set and the MPMAT or
LCDET bit is set, the PME pin will
always be asserted regardless of
the state of the PME_EN bit.
These bits are read/write accessi-
ble only when either the STOP bit
or the SPND bit is set. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP bit.
set when the MII auto-polling log-
ic detects a change in link status
and the LCMODE bit is set.
LCDET is cleared when power is
initially applied (POR).
This bit is always read/write
accessible.
this bit is set to 1, the LCDET bit gets
set when the MII auto polling logic
detects a Link Change.
Read/Write accessible only when
either the STOP bit or the SPND
bit is set. Cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Pattern Matched. This bit is set
when the PMMODE bit is set and
an OnNow pattern match occurs.
PMAT is cleared when power is
initially applied (POR).
This bit is read accessible always.
Magic Packet Physical Logical Broad-
cast Accept. If both EMPPLBA and
MPPLBA (CSR5, bit 5) are at their de-
fault value of 0, the Am79C978A con-
troller will only detect a Magic Packet
frame if the destination address of the
Am79C978A
5
4 MPPEN
3-1
0 RST_POL
MPMAT
RES
Magic Packet Match. This bit is
packet matches the content of the
physical address register (PADR). If ei-
ther EMPPLBA or MPPLBA is set to 1,
the destination address of the Magic
Packet frame can be unicast, multi-
cast, or broadcast. Note that the set-
ting of EMPPLBA and MPPLBA only
affects the address detection of the
Magic Packet frame. The Magic Pack-
et frame’s data sequence must be
made up of 16 consecutive physical
addresses (PADR[47:0]) regardless of
what kind of destination address it has.
This bit is always read/write ac-
cessible. EMPPLBA is set to 0 by
H_RESET or S_RESET and is not
affected by setting the STOP bit.
set when the integrated Ethernet
controller detects a Magic Packet
while it is in Magic Packet mode.
MPMAT is cleared when power is
initially applied (POR).
This bit is always read/write
accessible.
Magic Packet Pin Enable. When
this bit is set, the device enters
the Magic Packet mode when the
PG input goes LOW or MPEN bit
(CSR5, bit 2) gets set to 1. This
bit is OR’ed with MPEN bit
(CSR5, bit 2).
Read/Write accessible only when
either the STOP bit or the SPND
bit is set. Cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Reserved locations.
PHY_RST Pin Polarity. If the
PHY_POL is set to 1, the
PHY_RST pin is active LOW;
otherwise PHY_RST is active
HIGH.
This bit is read/write accessible
only when either the STOP bit or
the PND bit is set. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP bit.