AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 132

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

132
tries. When cleared, this bit
indicates that the Am79C978A
controller utilizes 16-bit software
structures for the initialization
block and the transmit and re-
ceive descriptor entries. In this
mode, the Am79C978A controller
is backwards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
The value of SSIZE32 is deter-
mined by the Am79C978A con-
troller according to the setting of
the Software Style (SWSTYLE,
bits 7-0 of this register).
Read
SSIZE32 is read only; write oper-
ations will be ignored. SSIZE32
will be cleared after H_RESET
(since SWSTYLE defaults to 0)
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be used
to generate values for the upper 8
bits of the 32-bit address bus dur-
ing master accesses initiated by
the Am79C978A controller. This
action is required because the 16-
bit software structures specified by
the SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C978A controller bus master
accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the Am79C978A controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C978A
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
accessible
always.
Am79C978A
7-0
SWSTYLE
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
Software Style register. The val-
ue in this register determines the
style of register and memory re-
sources that shall be used by the
Am79C978A controller. The Soft-
ware Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
All Am79C978A controller CSR
bits and BCR bits and all descrip-
tor, buffer, and initialization block
entries not cited in Table 32 are
unaffected by the Software Style
selection and are, therefore, al-
ways fully functional as specified
in the CSR and BCR sections.
These bits are read/write ac-
cessible only when either the
STOP or the SPND bit is set.
The SWSTYLE register will
contain the value 00h following
H_RESET and will be unaffect-
ed by S_RESET or STOP.