AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 155

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

11
NOUFLO
No Underflow on Transmit. When
For an adapter card application,
the value used for clock period
should be 30 ns to guarantee cor-
rect interface timing at the maxi-
mum clock frequency of 33 MHz.
These bits are read accessible
always; write accessible only
when the STOP bit is set.
ROMTMG is set to the value of
1001b by H_RESET and is not
affected by S_RESET or STOP.
The default value allows using
an Expansion ROM with an ac-
cess time of 250 ns in a system
with a maximum clock frequency
of 33 MHz.
the NOUFLO bit is set to 1, the
Am79C978A controller will not
start transmitting the preamble for
a packet until the Transmit Start
Point (CSR80, bits 10-11) require-
ment (except when XMTSP = 3h,
Full Packet has no meaning when
NOUFLO is set to 1) has been met
and the complete packet has been
DMA’d into the Am79C978A con-
troller. The complete packet may
reside in any combination of the
Bus Transmit FIFO, the SRAM,
and the MAC Transmit FIFO as
long as enough of the packet is in
the MAC Transmit FIFO to meet
the Transmit Start Point require-
ment. When the NOUFLO bit is
cleared to 0, the Transmit Start
Point is the only restriction on
when preamble transmission be-
gins for transmit packets.
Setting the NOUFLO bit guaran-
tees that the Am79C978A con-
troller will never suffer transmit
underflows, because the arbiter
that controls transfers to and from
the SRAM guarantees a worst
case latency on transfers to and
from the MAC and Bus Transmit
FIFOs such that it will never un-
derflow if the complete packet
has
Am79C978A controller before
packet transmission begins.
The NOUFLO bit has no effect
when the Am79C978A controller
been
DMA’d
into
Am79C978A
the
10
9
8
RES
MEMCMD
EXTREQ
Memory Command used for burst
Extended Request. This bit con-
is operating in the NO-SRAM
mode.
Read/Write accessible only when
either the STOP or the SPND bit
is set. NOUFLO is cleared to 0 af-
ter H_RESET or S_RESET and
is unaffected by STOP.
Reserved location. Written as
zero and read as undefined.
read accesses to the transmit
buffer. When MEMCMD is set to
0, all burst read accesses to the
transmit buffer are of the PCI
command type Memory Read
Line (type 14). When MEMCMD
is set to 1, all burst read accesses
to the transmit buffer are of the
PCI command type Memory
Read Multiple (type 12).
This bit is read accessible al-
ways; write accessible only when
either the STOP or the SPND bit
is set. MEMCMD is cleared by
H_RESET and is not affected by
S_RESET or STOP.
trols the deassertion of REQ for a
burst transaction. If EXTREQ is
set to 0, REQ is deasserted at the
beginning of a burst transaction.
(The Am79C978A controller nev-
er performs more than one burst
transaction within a single bus
mastership period.) In this mode,
the Am79C978A controller relies
on the PCI latency timer to get
enough bus bandwidth, in case
the system arbiter also removes
GNT at the beginning of the burst
transaction. If EXTREQ is set to
1, REQ stays asserted until the
last but one data phase of the
burst transaction is done. This
mode is useful for systems that
implement an arbitration scheme
without preemption and require
that REQ stays asserted through-
out the transaction.
EXTREQ should not be set to 1
when the Am79C978A controller
is used in a PCI bus application.
155