AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 86
AM79C978A
Manufacturer Part Number
AM79C978A
Description
Single-Chip 1/10 Mbps PCI Home Networking Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C978A.pdf
(256 pages)
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The LED pins can be configured to operate in either open-
drain mode (active low) or in totem-pole mode (active
high). The output can be stretched to allow the human
eye to recognize even short events that last only several
microseconds. After H_RESET, the five LED outputs are
configured as shown in Table 20.
For each LED register, each of the status signals is AND’d
with its enable signal, and these signals are all OR’d to-
gether to form a combined status signal. Each LED pin
combined status signal can be programmed to run to a
pulse stretcher, which consists of a 3-bit shift register
clocked at 38 Hz (26 ms). The data input of each shift reg-
ister is normally at logic 0. The OR gate output for each
LED register asynchronously sets all three bits of its shift
register when the output becomes asserted. The inverted
output of each shift register is used to control an LED pin.
Thus, the pulse stretcher provides two to three clocks of
stretched LED output, or 52 ms to 78 ms. See Figure 46.
Power Savings Mode
Power Management Support
The controller supports power management as defined in
the PCI Bus Power Management Interface Specification
V1.1 and Network Device Class Power Management Ref-
erence Specification V1.0a.These specifications define
the network device power states, PCI power manage-
ment interface including the Capabilities Data Structure
and power management registers block definitions,
power management events, and OnNow network wake-
up events.
The general scheme for the Am79C978A power manage-
ment is that when a PCI wake-up event is detected, a sig-
nal is generated to cause hardware external to the
Am79C978A device to put the computer into the working
(S0) mode.
86
Output
LED0
LED1
LED2
LED3
LED4
LED
Table 20. LED Default Configuration
Link Status
Indication
Transmit
Receive
Speed
Status
Power
Status
Driver Mode
Open Drain -
Open Drain -
Open Drain -
Open Drain -
Open Drain -
Active Low
Active Low
Active Low
Active Low
Active Low
Pulse Stretch
Enabled
Enabled
Enabled
Enabled
Enabled
Am79C978A
The Am79C978A device supports three types of wake-up
events:
1. Magic Packet Detect
2. OnNow Pattern Match Detect
3. Link State Change
Figure 47 shows the relationship between these wake-
up events and the various outputs used to signal to the
external hardware.
OnNow Wake-Up Sequence
The system software enables the PME pin by setting the
PME_EN bit in the PMCSR register (PCI configuration
registers, offset 44h, bit 8) to 1. When a wake-up event is
detected, the controller sets the PME_STATUS bit in the
PMCSR register (PCI configuration registers, offset 44h,
bit 15). Setting this bit causes the PME signal to be as-
serted. Assertion of the PME signal causes external hard-
ware to wake up the CPU. The system software then
reads the PMCSR register of every PCI device in the sys-
tem to determine which device asserted the PME signal.
When the software determines that the signal came
from the controller, it writes to the device's PMCSR to
put the device into power state D0. The software then
writes a 0 to the PME_STATUS bit to clear the bit and
turn off the PME signal, and it calls the device's software
driver to tell it that the device is now in state D0. The sys-
tem software can clear the PME_STATUS bit either be-
fore, after, or at the same time that it puts the device
back into the D0 state.
MR_SPEED_SEL
POWERE
POWER
RCVME
FDLSE
LNKSE
RCVM
RCVE
XMTE
MPSE
COLE
FDLS
LNKS
100E
MPS
COL
RCV
XMT
Figure 46. LED Control Logic
22399A-49
Pulse
Stretcher
To
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