AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 135

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR76: Receive Ring Length
Bit
31-16 RES
15-0
CSR78: Transmit Ring Length
Bit
31-16 RES
15-0
RCVRL
XMTRL
Name
Name
Transmit Ring Length. Contains
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
Receive Ring Length. Contains
the two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
Am79C978A controller’s initial-
ization routine based on the value
in the RLEN field of the initializa-
tion block. However, this register
can be manually altered. The ac-
tual receive ring length is defined
by the current value in this regis-
ter. The ring length can be de-
fined as any value from 1 to
65535.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
the two's complement of the
transmit descriptor ring length.
This register is initialized during
the Am79C978A controller’s ini-
tialization routine based on the
value in the TLEN field of the ini-
tialization block. However, this
register can be manually al-
tered. The actual transmit ring
length is defined by the current
value in this register. The ring
length can be defined as any
value from 1 to 65535.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
Description
Description
Am79C978A
CSR80: DMA Transfer Counter and FIFO Threshold
Control
Bit
31-16 RES
15-14 RES
13-12 RCVFW[1:0] Receive
Name
Reserved locations. Written as
Reserved locations. Written as
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
zeros and read as undefined.
RCVFW controls the point at
which receive DMA is requested
in relation to the number of re-
ceived bytes in the Receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been verified
as a non-runt) before receive
DMA is requested. Note, howev-
er, that if the network interface is
operating in half-duplex mode, in
order for receive DMA to be per-
formed for a new frame at least
64 bytes must have been re-
ceived. This effectively avoids
having to react to receive frames
which are runts or suffer a colli-
sion during the slot time (512 bit
times). If the Runt Packet Accept
feature is enabled or if the net-
work interface is operating in full-
duplex mode, receive DMA will
be requested as soon as either
the RCVFW threshold is reached
or a complete valid receive frame
is detected (regardless of length).
When the FDRPAD (BCR9, bit 2)
is set and the Am79C978A con-
troller is in full-duplex mode, in or-
der for receive DMA to be
performed for a new frame at
least 64 bytes must have been re-
ceived. This effectively disables
the runt packet accept feature in
full duplex.
When operating in the NO-SRAM
mode (no SRAM enabled), the
Bus Receive FIFO and the MAC
Receive operate like a single
FIFO and the watermark value
selected by RCVFW[1:0] sets the
number of bytes that must be
Description
FIFO
Watermark.
135