isp1583 NXP Semiconductors, isp1583 Datasheet - Page 98

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. POR timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 11. Clock with respect to the external POR . . . . . . . .23
Fig 12. ISP1583 with a 3.3 V supply . . . . . . . . . . . . . . . .24
Fig 13. Power-sharing mode . . . . . . . . . . . . . . . . . . . . . .25
Fig 14. Interrupt pin status during power off in
Fig 15. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .27
Fig 16. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .28
Fig 17. Programmable strobe timing . . . . . . . . . . . . . . . .59
Fig 18. Source differential data-to-EOP transition
Fig 19. Receiver differential data jitter . . . . . . . . . . . . . . .70
Fig 20. Receiver SE0 width tolerance . . . . . . . . . . . . . . .70
Fig 21. ISP1583 register access timing: separate
Fig 22. ISP1583 ready signal timing . . . . . . . . . . . . . . . .72
Fig 23. ISP1583 register access timing: separate
Fig 24. ISP1583 ready signal timing . . . . . . . . . . . . . . . .73
Fig 25. EOT timing in generic processor mode . . . . . . . .74
Fig 26. ISP1583 register access timing: multiplexed
Fig 27. ISP1583 register access timing: multiplexed
Fig 28. ISP1583 register access timing: multiplexed
Fig 29. ISP1583 register access timing: multiplexed
Fig 30. EOT timing in split bus mode . . . . . . . . . . . . . . . .79
Fig 31. PIO mode timing . . . . . . . . . . . . . . . . . . . . . . . . .81
Fig 32. GDMA slave mode timing: DIOR (master) and
Fig 33. GDMA slave mode timing: DIOR (master) or
Fig 34. GDMA slave mode timing: DACK (master and
ISP1583_6
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration ISP1583BS (top view) . . . . . . . .5
Pin configuration ISP1583ET (top view) . . . . . . . .5
Pin configuration ISP1583ET1 (top view) . . . . . . .6
Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Behavior of bit GLINTENA . . . . . . . . . . . . . . . . . .21
Resistor and electrolytic or tantalum capacitor
needed for V
Oscilloscope reading: no resistor and
capacitor in the network . . . . . . . . . . . . . . . . . . . .22
Oscilloscope reading: with resistor and
capacitor in the network . . . . . . . . . . . . . . . . . . . .22
power-sharing mode . . . . . . . . . . . . . . . . . . . . . .25
skew and EOP width . . . . . . . . . . . . . . . . . . . . . .69
address and data buses (8051 mode) . . . . . . . . .71
address and data buses (Freescale mode) . . . . .73
address/data bus (8051 mode) . . . . . . . . . . . . . .75
address/data bus (Freescale mode) . . . . . . . . . .76
address/data bus (A0 function and 8051 mode) .77
address/data bus (A0 function and Freescale
mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
DIOW (slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
DACK (slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
BUS
sensing . . . . . . . . . . . . . . . . . . .22
Rev. 06 — 20 August 2007
Fig 35. MDMA master mode timing. . . . . . . . . . . . . . . . . 84
Fig 36. Typical interface connections for generic
Fig 37. Typical interface connections for split bus
Fig 38. Load impedance for the DP and DM pins
Fig 39. Package outline SOT804-1 (HVQFN64) . . . . . . . 87
Fig 40. Package outline SOT543-1 (TFBGA64) . . . . . . . 88
Fig 41. Package outline SOT969-1 (TFBGA64) . . . . . . . 89
Fig 42. Temperature profiles for large and small
slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
processor mode. . . . . . . . . . . . . . . . . . . . . . . . . . 85
mode (slave mode) . . . . . . . . . . . . . . . . . . . . . . . 85
(full-speed mode) . . . . . . . . . . . . . . . . . . . . . . . . 86
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1583
continued >>
98 of 100