isp1583 NXP Semiconductors, isp1583 Datasheet - Page 21

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
7.14.2 Interrupt control
7.15 V
Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior
of this bit is given in
The following illustrations are only applicable for level trigger.
Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA
set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in
the corresponding Interrupt register bit.
Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the
Interrupt register is already set.
Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The
bold line shows the desired behavior of pin INT.
De-assertion of pin INT can be achieved either by clearing all the bits in the Interrupt
register or the DMA Interrupt Reason register, depending on the event.
Remark: When clearing an interrupt event, perform write to all the bytes of the register.
For more information on interrupt control, see
Section
The V
with bit CLKAON set to logic 0 (clock off option).
To detect whether the host is connected or not, that is V
a 1 F electrolytic or tantalum capacitor must be added to damp the overshoot on plug in.
Fig 6. Behavior of bit GLINTENA
BUS
BUS
sensing
8.5.1.
Pin INT: HIGH = de-assert; LOW = assert (individual interrupts are enabled).
pin is one of the ways to wake up the clock when the ISP1583 is suspended
INT pin
occurs, for example,
Figure
an interrupt event
(during this time,
GLINTENA = 0
Rev. 06 — 20 August 2007
SOF asserted)
6.
A
GLINTENA = 1
SOF asserted
B
Section
Hi-Speed USB Peripheral Controller
8.2.2,
BUS
GLINTENA = 0
SOF asserted
sensing, a 1 M resistor and
Section 8.2.5
C
004aaa394
© NXP B.V. 2007. All rights reserved.
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