isp1583 NXP Semiconductors, isp1583 Datasheet - Page 9

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
ISP1583_6
Product data sheet
Symbol
AD6
AD7
VCC1V8
n.c.
MODE1
DGND
ALE/A0
DATA0
DATA1
DATA2
DATA3
[1]
[4]
Pin description
Pin
30
31
32
33
34
35
36
37
38
39
40
ISP1583BS ISP1583ET ISP1583ET1
…continued
J8
K9
K10
-
J10
H9
H10
G9
G10
F9
F10
H6
H7
H8
-
G8
F8
F7
F6
E6
E7
E8
Rev. 06 — 20 August 2007
Type
I/O
I/O
-
-
I
-
I
I/O
I/O
I/O
I/O
[2]
Description
bit 6 of the multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V
tolerant
bit 7 of the multiplexed address and data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V
tolerant
voltage regulator output (1.8 V
voltage from the internal regulator; this regulated
voltage cannot drive external devices; decouple this
pin using a 0.1 F capacitor; see
not connected
mode selection input 1; used in split bus mode only:
Remark: When operating in generic processor mode,
set pin MODE1 as HIGH.
input pad; TTL; 5 V tolerant
digital ground
Address latch enable input — When pin MODE1 =
LOW during power-up, a falling edge on this pin
latches the address on the multiplexed address and
data bus AD[7:0].
Address and data selection input — When pin
MODE1 = HIGH during power-up, the function is
determined by the level on this pin (detected on the
rising edge of the WR_N pulse):
Remark: When operating in generic processor mode
with pin MODE1 = HIGH, this pin must be pulled down
using a 10 k resistor.
input pad; TTL; 5 V tolerant
bit 0 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V
tolerant
bit 1 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V
tolerant
bit 2 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V
tolerant
bit 3 of the bidirectional data bus
bidirectional pad; 4 ns slew-rate control; TTL; 5 V
tolerant
•
•
•
•
LOW: ALE function (address latch enable)
HIGH (connect to V
(address/data indicator)
bus mode only
HIGH: bus AD[7:0] is a register address
LOW: bus AD[7:0] is register data; used in split
Hi-Speed USB Peripheral Controller
CC(I/O)
): A0 function
0.15 V); tapped out
Section 7.17
© NXP B.V. 2007. All rights reserved.
ISP1583
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