isp1583 NXP Semiconductors, isp1583 Datasheet - Page 52

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
8.4.4 DMA Hardware register (address: 3Ch)
Table 55.
[1]
[2]
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Bit
15 to 14
13
12 to 11
10 to 8
7
6 to 4
3 to 2
1
0
The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is,
after configuring the DMA Configuration register).
PIO read or write that started using DMA Command register only performs 16-bit transfer.
Symbol
-
ATA_MODE
DMA_MODE
[1:0]
PIO_MODE
[2:0]
DIS_XFER_
CNT
-
MODE[1:0]
-
WIDTH
DMA Configuration register: bit description
[2]
Rev. 06 — 20 August 2007
Description
reserved
ATA Mode: Mode selection of the DMA core.
0 — Configures the DMA core for non-ATA mode. Used when issuing
DMA commands 00h and 01h.
1 — Configures the DMA core for ATA or MDMA mode. Used when
issuing DMA commands 02h to 07h, 0Ah and 0Ch; also used when
directly accessing Task File registers.
DMA Mode: These bits affect the timing for MDMA mode.
00 — MDMA mode 0: ATA(PI) compatible timing
01 — MDMA mode 1: ATA(PI) compatible timing
10 — MDMA mode 2: ATA(PI) compatible timing
11 — MDMA mode 3: enables the DMA Strobe Timing register (see
Table 76
MDMA mode
PIO Mode: These bits affect the PIO timing.
000 to 100 — PIO mode 0 to 4: ATA(PI) compatible timing
101 to 111 — reserved
Disable Transfer Count: Logic 1 disables the DMA Transfer Counter
(see
slave mode; in master mode the counter is always enabled.
reserved
Mode: These bits only affect GDMA (slave) and MDMA (master)
handshake signals.
00 — DIOR (master) or DIOW (slave): strobes data from the DMA bus
into the ISP1583; DIOW (master) or DIOR (slave): puts data from the
ISP1583 on the DMA bus.
01 — DIOR (master) or DACK (slave): strobes data from the DMA bus
into the ISP1583; DACK (master) or DIOR (slave): puts data from the
ISP1583 on the DMA bus.
10 — DACK (master and slave): strobes data from the DMA bus into the
ISP1583 and also puts data from the ISP1583 on the DMA bus.
11 — reserved
reserved
Width: This bit selects the DMA bus width for GDMA (slave) and MDMA
(master).
0 — 8-bit data bus.
1 — 16-bit data bus
Table
and
52). The transfer counter can be disabled only in GDMA
[1]
Table
77) for non-standard strobe durations; only used in
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1583
Table
52 of 100
56.