isp1583 NXP Semiconductors, isp1583 Datasheet - Page 54

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 60.
CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Task File 1F0 register (address: 40h): bit allocation
8.4.5 Task File registers (addresses: 40h to 4Fh)
R/W
7
0
0
These registers allow direct access to the internal registers of an ATAPI peripheral using
PIO mode. The supported Task File registers and their functions are shown in
The correct peripheral register is automatically addressed using pins CS1_N, CS0_N,
DA2, MODE0/DA1 and BUS_CONF/DA0 (see
Table 58.
Table 59.
In 8-bit bus mode, 16-bit Task File register 1F0 requires two consecutive write/read
accesses before the proper PIO write/read is generated on the IDE interface. The first
byte is always the lower byte (LSByte). Other Task File registers can directly be accessed.
Writing to Task File registers can be done in any order except for the Task File register
1F7, which must be written last.
Task file
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
3F6
3F7
Task file
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
3F6
3F7
R/W
6
0
0
Task File register functions
ATAPI peripheral register addressing
ATA function
data (16-bit)
error/feature
sector count
sector number/LBA[7:0]
cylinder low/LBA[15:8]
cylinder high/LBA[23:16]
drive/head/LBA[27:24]
command
alternate status/command
drive address
CS1_N
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
R/W
5
0
0
Rev. 06 — 20 August 2007
data (ATA or ATAPI)
R/W
CS0_N
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
4
0
0
R/W
3
0
0
Table
DA2
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Hi-Speed USB Peripheral Controller
59).
ATAPI function
data (16-bit)
error/feature
interrupt reason
reserved
cylinder low
cylinder high
drive select
status/command
alternate status/command
reserved
MODE0/DA1
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
R/W
2
0
0
R/W
1
0
0
BUS_CONF/DA0
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
© NXP B.V. 2007. All rights reserved.
ISP1583
Table
R/W
54 of 100
0
0
0
58.