isp1583 NXP Semiconductors, isp1583 Datasheet - Page 36

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
Table 29.
[1]
Bit
7 to 6
5
4
3
2
1
0
No interrupt is designed for OTG. The V
pulsing.
When OTG is in progress, the V
threshold or the OTG host has turned on the V
during SRP, the device must complete data-line pulsing and V
B_SESSION_VALID detection.
OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it
must provide a switch circuit to supply power to the ISP1583 core during SRP.
Symbol Description
-
DP
BSESS
VALID
INIT
COND
DISCV
VP
OTG
OTG register: bit description
reserved
Data Pulsing: Used for data-line pulsing to toggle DP to generate the required
data-line pulsing signal. The default value of this bit is logic 0. This bit must be
cleared when data-line pulsing is completed.
B-Session Valid: The device can initiate another V
after data-line pulsing and V
a session valid.
This bit is latched to logic 1 once V
threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The
ISP1583 continuously updates this bit to logic 1 when the B-session is valid. If
the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1583).
0 — It implies that SRP has failed. To proceed to a normal operation, the device
can restart SRP, clear bit OTG or proceed to an error handling process.
1 — It implies that the B-session is valid. The device clears bit OTG, goes into
normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register.
The OTG host has a maximum of 5 s before it responds to a session request.
During this period, the ISP1583 may request to suspend. Therefore, the device
firmware must wait for some time if it wishes to know the SRP result (success: if
there is minimum response from the host within 5 s; failure: if there is no
response from the host within 5 s).
Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and
check the bit status. If it reads logic 0, it means that V
0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then
start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP
is violated. So, the device must abort SRP.
The bit is set to logic 1 by the ISP1583 when initial conditions are not met, and
only writing logic 1 clears the bit. (If initial conditions are not met after this bit
has been cleared, it will be set again).
Remark: This implementation does not cover the case if an initial SRP condition
is violated when this bit is read and data-line pulsing is started.
Discharge V
before starting a new SRP. The discharge can take as long as 30 ms for V
be charged less than 0.8 V. This bit must be cleared (write logic 0) before a
session end.
V
V
cleared before 26 ms.
On-The-Go:
1 — Enables the OTG function. The V
0 — Normal operation. All OTG control bits will be masked. Status bits are
undefined.
BUS
BUS
pulsing signal. This bit must be set for more than 16 ms and must be
Pulsing: Used for V
Rev. 06 — 20 August 2007
[1]
BUS
BUS
: Set to logic 1 to discharge V
interrupt may be set because V
BUS
interrupt, however, may assert as a side effect during the V
BUS
BUS
BUS
pulsing to toggle VP to generate the required
supply to the device. Even if the V
pulsing, and before it clears this bit and detects
BUS
Hi-Speed USB Peripheral Controller
BUS
exceeds the B-device session valid
BUS
sensing functionality will be disabled.
pulsing before starting the
BUS
BUS
is charged over the V
. The device discharges V
BUS
BUS
discharge sequence
remains lower than
© NXP B.V. 2007. All rights reserved.
BUS
ISP1583
interrupt is found
BUS
sensing
36 of 100
BUS
BUS
BUS
to