isp1583 NXP Semiconductors, isp1583 Datasheet - Page 44

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isp1583

Manufacturer Part Number
isp1583
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 41.
Table 43.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Buffer Status register: bit allocation
Endpoint MaxPacketSize register: bit allocation
8.3.6 Endpoint MaxPacketSize register (address: 04h)
R/W
15
7
7
0
0
-
-
-
-
-
-
Table 41
Table 42.
This register determines the maximum packet size for all endpoints, except control 0. The
register contains 2 bytes, and the bit allocation is given in
Each time the register is written, the Buffer Length register of the corresponding endpoint
is re-initialized to the FFOSZ field value. Bits NTRANS control the number of transactions
allowed in a single micro frame (for high-speed isochronous and interrupt endpoints only).
Bit
7 to 2
1 to 0
reserved
R/W
14
6
6
0
0
-
-
-
-
-
-
shows the bit allocation of the Buffer Status register.
Symbol
-
BUF[1:0]
Buffer Status register: bit description
R/W
13
5
5
0
0
-
-
-
-
-
-
Rev. 06 — 20 August 2007
reserved
Description
reserved
Buffer:
00 — Buffers are not filled.
01 — One of the buffers is filled.
10 — One of the buffers is filled.
11 — Both the buffers are filled.
R/W
R/W
12
4
0
0
4
0
0
-
-
-
NTRANS[1:0]
FFOSZ[7:0]
R/W
R/W
11
3
0
0
3
0
0
-
-
-
Hi-Speed USB Peripheral Controller
R/W
R/W
10
2
0
0
2
0
0
-
-
-
Table
43.
FFOSZ[10:8]
BUF1
R/W
R/W
R
1
0
0
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
BUF0
R/W
R/W
44 of 100
R
0
0
0
8
0
0
0
0
0

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